From 0aada3cddb37e6f854420a06b565c7db64360650 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 24 Nov 2020 22:55:53 +0100 Subject: soc/amd: move bootblock inside main SoC directories There's no need to have the bootblock in its own sub-directory, so move it to each SoC's main directory to avoid clutter. This makes soc/amd more consistent with the coreboot code base in src/northbridge, src/southbridge and src/soc with the exception of src/soc/intel. Change-Id: I78a9ce1cd0d790250a66c82bb1d8aa6c3b4f7162 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47982 Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Makefile.inc | 2 +- src/soc/amd/picasso/bootblock.c | 149 ++++++++++++++++++++++++++ src/soc/amd/picasso/bootblock/bootblock.c | 149 -------------------------- src/soc/amd/stoneyridge/Makefile.inc | 2 +- src/soc/amd/stoneyridge/bootblock.c | 104 ++++++++++++++++++ src/soc/amd/stoneyridge/bootblock/bootblock.c | 104 ------------------ 6 files changed, 255 insertions(+), 255 deletions(-) create mode 100644 src/soc/amd/picasso/bootblock.c delete mode 100644 src/soc/amd/picasso/bootblock/bootblock.c create mode 100644 src/soc/amd/stoneyridge/bootblock.c delete mode 100644 src/soc/amd/stoneyridge/bootblock/bootblock.c (limited to 'src/soc/amd') diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index f010c7b055..b5e409b055 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -11,7 +11,7 @@ subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage -bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock.c bootblock-y += aoac.c bootblock-y += southbridge.c bootblock-y += i2c.c diff --git a/src/soc/amd/picasso/bootblock.c b/src/soc/amd/picasso/bootblock.c new file mode 100644 index 0000000000..0b52a17307 --- /dev/null +++ b/src/soc/amd/picasso/bootblock.c @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +asmlinkage void bootblock_resume_entry(void); + +/* PSP performs the memory training and setting up DRAM map prior to x86 cores + being released. Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise, + route lower memory addresses covered by fixed MTRRs to DRAM except for + 0xa0000-0xc0000 . */ +static void set_caching(void) +{ + msr_t top_mem; + msr_t sys_cfg; + msr_t mtrr_def_type; + msr_t fixed_mtrr_ram; + msr_t fixed_mtrr_mmio; + struct var_mtrr_context mtrr_ctx; + + var_mtrr_context_init(&mtrr_ctx, NULL); + top_mem = rdmsr(TOP_MEM); + /* Enable RdDram and WrDram attributes in fixed MTRRs. */ + sys_cfg = rdmsr(SYSCFG_MSR); + sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; + + /* Fixed MTRR constants. */ + fixed_mtrr_ram.lo = fixed_mtrr_ram.hi = + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 0) | + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 8) | + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 16) | + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 24); + fixed_mtrr_mmio.lo = fixed_mtrr_mmio.hi = + ((MTRR_TYPE_UNCACHEABLE) << 0) | + ((MTRR_TYPE_UNCACHEABLE) << 8) | + ((MTRR_TYPE_UNCACHEABLE) << 16) | + ((MTRR_TYPE_UNCACHEABLE) << 24); + + /* Prep default MTRR type. */ + mtrr_def_type = rdmsr(MTRR_DEF_TYPE_MSR); + mtrr_def_type.lo &= ~MTRR_DEF_TYPE_MASK; + mtrr_def_type.lo |= MTRR_TYPE_UNCACHEABLE; + mtrr_def_type.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN; + + disable_cache(); + + wrmsr(SYSCFG_MSR, sys_cfg); + + clear_all_var_mtrr(); + + var_mtrr_set(&mtrr_ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK); + var_mtrr_set(&mtrr_ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + /* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */ + wrmsr(MTRR_FIX_64K_00000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_16K_80000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_16K_A0000, fixed_mtrr_mmio); + wrmsr(MTRR_FIX_4K_C0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_C8000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_D0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_D8000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_E0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_E8000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_F0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_F8000, fixed_mtrr_ram); + + wrmsr(MTRR_DEF_TYPE_MSR, mtrr_def_type); + + /* Enable Fixed and Variable MTRRs. */ + sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn; + sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB; + /* AGESA currently expects SYSCFG_MSR_MtrrFixDramModEn to be set. Once + MP init happens in coreboot proper it can be knocked down. */ + wrmsr(SYSCFG_MSR, sys_cfg); + + enable_cache(); +} + +static void write_resume_eip(void) +{ + msr_t s3_resume_entry = { + .hi = (uint64_t)(uintptr_t)bootblock_resume_entry >> 32, + .lo = (uintptr_t)bootblock_resume_entry & 0xffffffff, + }; + + /* + * Writing to the EIP register can only be done once, otherwise a fault is triggered. + * When this register is written, it will trigger the microcode to stash the CPU state + * (crX , mtrrs, registers, etc) into the CC6 save area. On resume, the state will be + * restored and execution will continue at the EIP. + */ + if (!acpi_is_wakeup_s3()) + wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry); +} + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + set_caching(); + write_resume_eip(); + enable_pci_mmconf(); + + /* + * base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz + * when we use micro-seconds granularity for Zork + */ + base_timestamp /= tsc_freq_mhz(); + + if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + boot_with_psp_timestamp(base_timestamp); + + /* + * if VBOOT_STARTS_BEFORE_BOOTBLOCK is not selected or + * previous step did nothing, proceed with normal bootblock main. + */ + bootblock_main_with_basetime(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ + fch_pre_init(); +} + +void bootblock_soc_init(void) +{ + u32 val = cpuid_eax(1); + printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + + if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { + verify_psp_transfer_buf(); + show_psp_transfer_info(); + } + + fch_early_init(); +} diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c deleted file mode 100644 index 0b52a17307..0000000000 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -asmlinkage void bootblock_resume_entry(void); - -/* PSP performs the memory training and setting up DRAM map prior to x86 cores - being released. Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise, - route lower memory addresses covered by fixed MTRRs to DRAM except for - 0xa0000-0xc0000 . */ -static void set_caching(void) -{ - msr_t top_mem; - msr_t sys_cfg; - msr_t mtrr_def_type; - msr_t fixed_mtrr_ram; - msr_t fixed_mtrr_mmio; - struct var_mtrr_context mtrr_ctx; - - var_mtrr_context_init(&mtrr_ctx, NULL); - top_mem = rdmsr(TOP_MEM); - /* Enable RdDram and WrDram attributes in fixed MTRRs. */ - sys_cfg = rdmsr(SYSCFG_MSR); - sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; - - /* Fixed MTRR constants. */ - fixed_mtrr_ram.lo = fixed_mtrr_ram.hi = - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 0) | - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 8) | - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 16) | - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 24); - fixed_mtrr_mmio.lo = fixed_mtrr_mmio.hi = - ((MTRR_TYPE_UNCACHEABLE) << 0) | - ((MTRR_TYPE_UNCACHEABLE) << 8) | - ((MTRR_TYPE_UNCACHEABLE) << 16) | - ((MTRR_TYPE_UNCACHEABLE) << 24); - - /* Prep default MTRR type. */ - mtrr_def_type = rdmsr(MTRR_DEF_TYPE_MSR); - mtrr_def_type.lo &= ~MTRR_DEF_TYPE_MASK; - mtrr_def_type.lo |= MTRR_TYPE_UNCACHEABLE; - mtrr_def_type.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN; - - disable_cache(); - - wrmsr(SYSCFG_MSR, sys_cfg); - - clear_all_var_mtrr(); - - var_mtrr_set(&mtrr_ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK); - var_mtrr_set(&mtrr_ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); - - /* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */ - wrmsr(MTRR_FIX_64K_00000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_16K_80000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_16K_A0000, fixed_mtrr_mmio); - wrmsr(MTRR_FIX_4K_C0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_C8000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_D0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_D8000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_E0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_E8000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_F0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_F8000, fixed_mtrr_ram); - - wrmsr(MTRR_DEF_TYPE_MSR, mtrr_def_type); - - /* Enable Fixed and Variable MTRRs. */ - sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn; - sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB; - /* AGESA currently expects SYSCFG_MSR_MtrrFixDramModEn to be set. Once - MP init happens in coreboot proper it can be knocked down. */ - wrmsr(SYSCFG_MSR, sys_cfg); - - enable_cache(); -} - -static void write_resume_eip(void) -{ - msr_t s3_resume_entry = { - .hi = (uint64_t)(uintptr_t)bootblock_resume_entry >> 32, - .lo = (uintptr_t)bootblock_resume_entry & 0xffffffff, - }; - - /* - * Writing to the EIP register can only be done once, otherwise a fault is triggered. - * When this register is written, it will trigger the microcode to stash the CPU state - * (crX , mtrrs, registers, etc) into the CC6 save area. On resume, the state will be - * restored and execution will continue at the EIP. - */ - if (!acpi_is_wakeup_s3()) - wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry); -} - -asmlinkage void bootblock_c_entry(uint64_t base_timestamp) -{ - set_caching(); - write_resume_eip(); - enable_pci_mmconf(); - - /* - * base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz - * when we use micro-seconds granularity for Zork - */ - base_timestamp /= tsc_freq_mhz(); - - if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) - boot_with_psp_timestamp(base_timestamp); - - /* - * if VBOOT_STARTS_BEFORE_BOOTBLOCK is not selected or - * previous step did nothing, proceed with normal bootblock main. - */ - bootblock_main_with_basetime(base_timestamp); -} - -void bootblock_soc_early_init(void) -{ - fch_pre_init(); -} - -void bootblock_soc_init(void) -{ - u32 val = cpuid_eax(1); - printk(BIOS_DEBUG, "Family_Model: %08x\n", val); - - if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { - verify_psp_transfer_buf(); - show_psp_transfer_info(); - } - - fch_early_init(); -} diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 311ea6886b..8cdf6ccdbe 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -12,7 +12,7 @@ subdirs-y += ../../../cpu/x86/smm bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c bootblock-y += BiosCallOuts.c -bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock.c bootblock-y += gpio.c bootblock-y += i2c.c bootblock-y += enable_usbdebug.c diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c new file mode 100644 index 0000000000..4025f80c96 --- /dev/null +++ b/src/soc/amd/stoneyridge/bootblock.c @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if CONFIG_PI_AGESA_TEMP_RAM_BASE < 0x100000 +#error "Error: CONFIG_PI_AGESA_TEMP_RAM_BASE must be >= 1MB" +#endif +#if CONFIG_PI_AGESA_CAR_HEAP_BASE < 0x100000 +#error "Error: CONFIG_PI_AGESA_CAR_HEAP_BASE must be >= 1MB" +#endif + +/* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */ +static void amd_initmmio(void) +{ + msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); + int mtrr; + + /* + * todo: AGESA currently writes variable MTRRs. Once that is + * corrected, un-hardcode this MTRR. + * + * Be careful not to use get_free_var_mtrr/set_var_mtrr pairs + * where all cores execute the path. Both cores within a compute + * unit share MTRRs. Programming core0 has the appearance of + * modifying core1 too. Using the pair again will create + * duplicate copies. + */ + mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH; + set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_CAR_HEAP; + set_var_mtrr(mtrr, CONFIG_PI_AGESA_CAR_HEAP_BASE, + CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK); + + mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_TEMPRAM; + set_var_mtrr(mtrr, CONFIG_PI_AGESA_TEMP_RAM_BASE, + CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_UNCACHEABLE); +} + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + enable_pci_mmconf(); + amd_initmmio(); + /* + * Call lib/bootblock.c main with BSP, shortcut for APs + */ + if (!boot_cpu()) { + void (*ap_romstage_entry)(void) = + (void (*)(void))get_ap_entry_ptr(); + + ap_romstage_entry(); /* execution does not return */ + halt(); + } + + /* TSC cannot be relied upon. Override the TSC value passed in. */ + bootblock_main_with_basetime(timestamp_get()); +} + +void bootblock_soc_early_init(void) +{ + /* + * This call (sb_reset_i2c_slaves) was originally early at + * bootblock_c_entry, but had to be moved here. There was an + * unexplained delay in the middle of the i2c transaction when + * we had it in bootblock_c_entry. Moving it to this point + * (or adding delays) fixes the issue. It seems like the processor + * just pauses but we don't know why. + */ + sb_reset_i2c_slaves(); + bootblock_fch_early_init(); + post_code(0x90); +} + +void bootblock_soc_init(void) +{ + if (CONFIG(STONEYRIDGE_UART)) + assert(CONFIG_UART_FOR_CONSOLE >= 0 + && CONFIG_UART_FOR_CONSOLE <= 1); + + u32 val = cpuid_eax(1); + printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + + bootblock_fch_init(); + + /* Initialize any early i2c buses. */ + i2c_soc_early_init(); +} diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c deleted file mode 100644 index 4025f80c96..0000000000 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ /dev/null @@ -1,104 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if CONFIG_PI_AGESA_TEMP_RAM_BASE < 0x100000 -#error "Error: CONFIG_PI_AGESA_TEMP_RAM_BASE must be >= 1MB" -#endif -#if CONFIG_PI_AGESA_CAR_HEAP_BASE < 0x100000 -#error "Error: CONFIG_PI_AGESA_CAR_HEAP_BASE must be >= 1MB" -#endif - -/* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */ -static void amd_initmmio(void) -{ - msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); - int mtrr; - - /* - * todo: AGESA currently writes variable MTRRs. Once that is - * corrected, un-hardcode this MTRR. - * - * Be careful not to use get_free_var_mtrr/set_var_mtrr pairs - * where all cores execute the path. Both cores within a compute - * unit share MTRRs. Programming core0 has the appearance of - * modifying core1 too. Using the pair again will create - * duplicate copies. - */ - mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH; - set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); - - mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_CAR_HEAP; - set_var_mtrr(mtrr, CONFIG_PI_AGESA_CAR_HEAP_BASE, - CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK); - - mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_TEMPRAM; - set_var_mtrr(mtrr, CONFIG_PI_AGESA_TEMP_RAM_BASE, - CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_UNCACHEABLE); -} - -asmlinkage void bootblock_c_entry(uint64_t base_timestamp) -{ - enable_pci_mmconf(); - amd_initmmio(); - /* - * Call lib/bootblock.c main with BSP, shortcut for APs - */ - if (!boot_cpu()) { - void (*ap_romstage_entry)(void) = - (void (*)(void))get_ap_entry_ptr(); - - ap_romstage_entry(); /* execution does not return */ - halt(); - } - - /* TSC cannot be relied upon. Override the TSC value passed in. */ - bootblock_main_with_basetime(timestamp_get()); -} - -void bootblock_soc_early_init(void) -{ - /* - * This call (sb_reset_i2c_slaves) was originally early at - * bootblock_c_entry, but had to be moved here. There was an - * unexplained delay in the middle of the i2c transaction when - * we had it in bootblock_c_entry. Moving it to this point - * (or adding delays) fixes the issue. It seems like the processor - * just pauses but we don't know why. - */ - sb_reset_i2c_slaves(); - bootblock_fch_early_init(); - post_code(0x90); -} - -void bootblock_soc_init(void) -{ - if (CONFIG(STONEYRIDGE_UART)) - assert(CONFIG_UART_FOR_CONSOLE >= 0 - && CONFIG_UART_FOR_CONSOLE <= 1); - - u32 val = cpuid_eax(1); - printk(BIOS_DEBUG, "Family_Model: %08x\n", val); - - bootblock_fch_init(); - - /* Initialize any early i2c buses. */ - i2c_soc_early_init(); -} -- cgit v1.2.3