From e09294f57a03a21ff89b571b0a606c358fc97188 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 17 Feb 2021 22:22:21 +0100 Subject: include/cpu/amd/msr: rename MSR_PSP_ADDR to PSP_ADDR_MSR The new name is more consistent with the rest of the MSR definitions. Signed-off-by: Felix Held Change-Id: I5666d9837c61881639b5f292553a728e49c5ceb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50855 Reviewed-by: Raul Rangel Reviewed-by: Marshall Dawson Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/cpu.c | 4 ++-- src/soc/amd/stoneyridge/psp.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src/soc/amd/stoneyridge') diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 17fd9b97bb..d943deb69a 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -76,10 +76,10 @@ static void model_15_init(struct device *dev) uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */ psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4); psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - psp_msr = rdmsr(MSR_PSP_ADDR); + psp_msr = rdmsr(PSP_ADDR_MSR); if (psp_msr.lo == 0) { psp_msr.lo = psp_bar; - wrmsr(MSR_PSP_ADDR, psp_msr); + wrmsr(PSP_ADDR_MSR, psp_msr); } } diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c index cd14d7bf69..8d6290f619 100644 --- a/src/soc/amd/stoneyridge/psp.c +++ b/src/soc/amd/stoneyridge/psp.c @@ -45,9 +45,9 @@ void *soc_get_mbox_address(void) /* Determine if Bar3Hide has been set, and if hidden get the base from * the MSR instead. */ if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) { - psp_mmio = rdmsr(MSR_PSP_ADDR).lo; + psp_mmio = rdmsr(PSP_ADDR_MSR).lo; if (!psp_mmio) { - printk(BIOS_WARNING, "PSP: BAR hidden, MSR_PSP_ADDR uninitialized\n"); + printk(BIOS_WARNING, "PSP: BAR hidden, PSP_ADDR_MSR uninitialized\n"); return 0; } } else { -- cgit v1.2.3