From 9e591c409a3e3264f54a3784b0891a7f27dd52d8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 9 Jan 2021 12:37:25 +0200 Subject: soc/amd: Refactor some ACPI S3 calls MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do not pass ACPI S3 state as a parameter, by locally calling acpi_is_wakeup_s3() compiler has better chance for optimizing HAVE_ACPI_RESUME=n case. Test for acpi_s3_allowed() is already included in the implementation of acpi_is_wakeup_s3() and is removed as redunandant. For ramstage, acpi_is_wakeup_s3() evaluates to romstage_handoff_if_resume(). Change-Id: I6c1e00ec3d5be9a47b9d911c73965bc0c2b17624 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/49838 Reviewed-by: Felix Held Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/chip.c | 5 +---- src/soc/amd/stoneyridge/include/soc/romstage.h | 8 -------- src/soc/amd/stoneyridge/northbridge.c | 3 +-- src/soc/amd/stoneyridge/romstage.c | 7 +++---- 4 files changed, 5 insertions(+), 18 deletions(-) delete mode 100644 src/soc/amd/stoneyridge/include/soc/romstage.h (limited to 'src/soc/amd/stoneyridge') diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index e8bc71a4c8..1282f3988c 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -138,9 +137,7 @@ struct chip_operations soc_amd_stoneyridge_ops = { static void earliest_ramstage(void *unused) { - int s3_resume = acpi_s3_resume_allowed() && - romstage_handoff_is_resume(); - if (!s3_resume) { + if (!acpi_is_wakeup_s3()) { post_code(0x46); if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2"); diff --git a/src/soc/amd/stoneyridge/include/soc/romstage.h b/src/soc/amd/stoneyridge/include/soc/romstage.h deleted file mode 100644 index 1cbaeec831..0000000000 --- a/src/soc/amd/stoneyridge/include/soc/romstage.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef AMD_STONEYRIDGE_ROMSTAGE_H -#define AMD_STONEYRIDGE_ROMSTAGE_H - -void mainboard_romstage_entry_s3(int s3_resume); - -#endif /* AMD_STONEYRIDGE_ROMSTAGE_H */ diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 0f66927e45..25e55a6bb5 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -408,7 +407,7 @@ void fam15_finalize(void *chip_info) void domain_enable_resources(struct device *dev) { /* Must be called after PCI enumeration and resource allocation */ - if (!romstage_handoff_is_resume()) + if (!acpi_is_wakeup_s3()) do_agesawrapper(AMD_INIT_MID, "amdinitmid"); } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 49279028b6..3db7c42e7f 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -20,13 +20,12 @@ #include #include #include -#include #include #include #include "chip.h" -void __weak mainboard_romstage_entry_s3(int s3_resume) +void __weak mainboard_romstage_entry(void) { /* By default, don't do anything */ } @@ -54,7 +53,7 @@ asmlinkage void car_stage_entry(void) msr_t base, mask; msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; - int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); + int s3_resume = acpi_is_wakeup_s3(); int i; console_init(); @@ -63,7 +62,7 @@ asmlinkage void car_stage_entry(void) if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) psp_load_named_blob(BLOB_SMU_FW, "smu_fw"); - mainboard_romstage_entry_s3(s3_resume); + mainboard_romstage_entry(); elog_boot_notify(s3_resume); bsp_agesa_call(); -- cgit v1.2.3