From 916cd50edc90bc9edd134d6a37911174cc0ff944 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 4 Aug 2021 17:22:36 +0200 Subject: soc/amd/*/bootblock,early_fch: rework i2c_scl_pins configuration drive_scl in soc/amd/common/block/i2c/i2c.c writes the raw GPIO MMIO configuration register and drives it as output, so don't initially configure the GPIO as input with no pull up/down. This is a preparation to use the common AMD GPIO access functions instead of the raw register accesses, since the gpio_set function only sets the output value, but doesn't reconfigure the direction. Using gpio_output there instead would reconfigure the direction as well, but would result in doubling the number of MMIO accesses, so just configure the GPIOs correctly right away to avoid that. TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook looks exactly the same as before during the reset_i2c_peripherals call. This was probed at the SCL pad of the unpopulated I2C level shifter on the side that is connected to the SoC. Signed-off-by: Felix Held Change-Id: I8e94afe0c755a02abcc722d5094e220d8781f8f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56807 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/bootblock.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/soc/amd/stoneyridge') diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c index fc4284f502..499ff633d4 100644 --- a/src/soc/amd/stoneyridge/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock.c @@ -28,12 +28,12 @@ #error "Error: CONFIG_PI_AGESA_CAR_HEAP_BASE must be >= 1MB" #endif -/* This table is for the initial conversion of all SCL pins to input with no pull. */ +/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */ static const struct soc_i2c_scl_pin i2c_scl_pins[] = { - { PAD_GPI(I2C0_SCL_PIN, PULL_NONE), GPIO_I2C0_SCL }, - { PAD_GPI(I2C1_SCL_PIN, PULL_NONE), GPIO_I2C1_SCL }, - { PAD_GPI(I2C2_SCL_PIN, PULL_NONE), GPIO_I2C2_SCL }, - { PAD_GPI(I2C3_SCL_PIN, PULL_NONE), GPIO_I2C3_SCL }, + { PAD_GPO(I2C0_SCL_PIN, HIGH), GPIO_I2C0_SCL }, + { PAD_GPO(I2C1_SCL_PIN, HIGH), GPIO_I2C1_SCL }, + { PAD_GPO(I2C2_SCL_PIN, HIGH), GPIO_I2C2_SCL }, + { PAD_GPO(I2C3_SCL_PIN, HIGH), GPIO_I2C3_SCL }, }; /* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */ -- cgit v1.2.3