From 638bd13a656e9bbf077d2ab3d707ea09e715d388 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Fri, 14 Sep 2018 10:16:40 -0600 Subject: amd/stoneyridge: Sync PSP base to MSR According to AMD, there exists an undocumented MSR which must be written with the PSP's base address. Read the value from the PSP's config space and sync each core's copy of the MSR to match. BUG=b:76167350 TEST=boot Grunt and verify "rdrand: disabled" goes away from dmesg Change-Id: I30027d3b0a6fbd540375e96001beb9c25bf3a678 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/28608 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/cpu.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'src/soc/amd/stoneyridge') diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 43ee6a029f..92b2950ad3 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -121,6 +121,23 @@ static void model_15_init(struct device *dev) { check_mca(); setup_lapic(); + + /* + * Per AMD, sync an undocumented MSR with the PSP base address. + * Experiments showed that if you write to the MSR after it has + * been previously programmed, it causes a general protection fault. + * Also, the MSR survives warm reset and S3 cycles, so we need to + * test if it was previously written before writing to it. + */ + msr_t psp_msr; + uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */ + psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4); + psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + psp_msr = rdmsr(0xc00110a2); + if (psp_msr.lo == 0) { + psp_msr.lo = psp_bar; + wrmsr(0xc00110a2, psp_msr); + } } static struct device_operations cpu_dev_ops = { -- cgit v1.2.3