From 615818f5a98d19079fd5e1725cd56786d39882c2 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Tue, 31 May 2022 21:33:43 +0200
Subject: soc/amd/*: Make mtrr decision based on syscfg

The syscfg has to option to automatically mark the range between 4G and
TOM2, which contains DRAM, as WB. Making it generally not necessary to
allocate MTRRs for memory above 4G if no PCI BARs are placed up there.

Change-Id: Ifbacae28e272ab2f39f268ad034354a9c590d035
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
---
 src/soc/amd/stoneyridge/cpu.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

(limited to 'src/soc/amd/stoneyridge')

diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 3cd3a9580a..e691a51b39 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -3,20 +3,21 @@
 #include <amdblocks/mca.h>
 #include <amdblocks/reset.h>
 #include <amdblocks/smm.h>
+#include <console/console.h>
 #include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/mp.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
-#include <soc/pci_devs.h>
 #include <soc/cpu.h>
+#include <soc/iomap.h>
 #include <soc/northbridge.h>
+#include <soc/pci_devs.h>
 #include <soc/smi.h>
-#include <soc/iomap.h>
-#include <console/console.h>
 #include <types.h>
 
 /*
@@ -32,7 +33,11 @@
  */
 static void pre_mp_init(void)
 {
-	x86_setup_mtrrs_with_detect();
+	const msr_t syscfg = rdmsr(SYSCFG_MSR);
+	if (syscfg.lo & SYSCFG_MSR_TOM2WB)
+		x86_setup_mtrrs_with_detect_no_above_4gb();
+	else
+		x86_setup_mtrrs_with_detect();
 	x86_mtrr_check();
 }
 
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