From 4f16049f17a4dcbf329d6b30f0d00f0a7f5490bf Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 23 May 2018 15:34:04 -0600 Subject: mb/google/kahlee/variants/grunt: Select low-power mode for BayHub720 Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to save power. This requires use of an additional register (Misc control register 2) and another bit in the existing 'protect' register. The naming of bit 0 of that register is incorrect, based on the latest datasheet (14 June 2018) so fix that too. BUG=b:73726008 BRANCH=none TEST=boot without this patch: iotools mem_read32 0xfed80e00 0x0046ffff With this patch: $ iotools mem_read32 0xfed80e00 0x00463fff Also see that the PCIe clock stops when eMMC is idle and can be started by starting disk activity. Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480 Signed-off-by: Simon Glass Reviewed-on: https://review.coreboot.org/26515 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Martin Roth --- src/soc/amd/stoneyridge/include/soc/southbridge.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/amd/stoneyridge') diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 77e4979698..3e70c32c25 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -356,6 +356,12 @@ #define PM1_LIMIT 16 #define GPE0_LIMIT 28 +/* Bit definitions for MISC_MMIO_BASE register GPPClkCntrl */ +#define GPP_CLK_CNTRL 0 +#define GPP_CLK2_CLOCK_REQ_MAP_SHIFT 8 +#define GPP_CLK2_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK2_CLOCK_REQ_MAP_SHIFT) +#define GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 3 + struct stoneyridge_aoac { int enable; int status; -- cgit v1.2.3