From 26935d1ecc3e92803de985473b1a124982a9e226 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 8 Dec 2020 00:40:04 +0100 Subject: soc/amd: factor out legacy I/O and cf9 decode enable functions Replace sb prefix with fch prefix, since those are all FCHs and no south bridges any more. Verstage on PSP uses the I/O access mechanism instead of the MMIO one, so keep a separate function for that, but also move it to the common mmio_util file to have them all in one place. Change-Id: I47dac9ee3d9e27f7b7a5fddab17cf4fc10de6c3e Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/48435 Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/southbridge.c | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) (limited to 'src/soc/amd/stoneyridge') diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 881570241a..ba23e90b58 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -200,20 +200,6 @@ static void sb_lpc_decode(void) lpc_enable_decode(tmp); } -static void sb_enable_cf9_io(void) -{ - uint32_t reg = pm_read32(PM_DECODE_EN); - - pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); -} - -static void sb_enable_legacy_io(void) -{ - uint32_t reg = pm_read32(PM_DECODE_EN); - - pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); -} - void sb_clk_output_48Mhz(u32 osc) { u32 ctrl; @@ -347,14 +333,14 @@ void bootblock_fch_early_init(void) sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ enable_acpimmio_decode_pm04(); fch_smbus_init(); - sb_enable_cf9_io(); + fch_enable_cf9_io(); setup_spread_spectrum(&reboot); setup_misc(&reboot); if (reboot) warm_reset(); - sb_enable_legacy_io(); + fch_enable_legacy_io(); enable_aoac_devices(); } -- cgit v1.2.3