From 2572153aefbb8def000cddea973c34be5829c63d Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Thu, 11 Jan 2018 16:14:39 -0800 Subject: soc/amd/stoneyridge: Add definition for GENINT_DISABLE BUG=b:71867096 TEST=None Change-Id: Ic8111d34355e6667c37a51d285ebb50c1659f4e5 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/23227 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/include/soc/southbridge.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/amd/stoneyridge') diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index bbf6344f6a..d9016bc427 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -93,6 +93,7 @@ #define PM_HUD_SD_FLASH_CTRL 0xe7 #define PM_YANG_SD_FLASH_CTRL 0xe8 #define PM_PCIB_CFG 0xea +#define PM_GENINT_DISABLE BIT(0) #define PM_LPC_GATING 0xec #define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_A20_EN BIT(1) -- cgit v1.2.3