From 21cde8b83227fa324f246672b1e2d58408ea6bf8 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Sun, 7 May 2017 16:47:36 -0600 Subject: soc/amd/stoneyridge: Add CPU files Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. This is the second patch in the process of converting Stoney Ridge to soc/. Changes: - update Kconfig and Makefiles - update vendorcode/amd for new soc/ path Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/19723 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/stoneyridge/Kconfig | 53 ++++++++++++- src/soc/amd/stoneyridge/Makefile.inc | 15 +++- src/soc/amd/stoneyridge/acpi/cpu.asl | 78 ++++++++++++++++++ src/soc/amd/stoneyridge/fixme.c | 97 +++++++++++++++++++++++ src/soc/amd/stoneyridge/model_15_init.c | 135 ++++++++++++++++++++++++++++++++ 5 files changed, 373 insertions(+), 5 deletions(-) create mode 100644 src/soc/amd/stoneyridge/acpi/cpu.asl create mode 100644 src/soc/amd/stoneyridge/fixme.c create mode 100644 src/soc/amd/stoneyridge/model_15_init.c (limited to 'src/soc/amd/stoneyridge') diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 4cd3116ecd..591037f4ab 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -13,14 +13,61 @@ ## GNU General Public License for more details. ## -config SOC_AMD_STONEYRIDGE +config SOC_AMD_STONEYRIDGE_FP4 bool + help + AMD Stoney Ridge FP4 support + +config SOC_AMD_STONEYRIDGE_FT4 + bool + help + AMD Stoney Ridge FT4 support + +if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 select IOAPIC select HAVE_USBDEBUG_OPTIONS select HAVE_HARD_RESET + select LAPIC_MONOTONIC_TIMER select SOC_AMD_COMMON + select SOC_AMD_PI + select SPI_FLASH if HAVE_ACPI_RESUME + select TSC_SYNC_LFENCE + select UDELAY_LAPIC + +config UDELAY_LAPIC_FIXED_FSB + int + default 200 + +# TODO: Sync these with definitions in PI vendorcode. +# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. +# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. -if SOC_AMD_STONEYRIDGE +config DCACHE_RAM_BASE + hex + default 0x30000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + +config CPU_ADDR_BITS + int + default 48 + +config CBB + hex + default 0x0 + +config CDB + hex + default 0x18 config BOOTBLOCK_SOUTHBRIDGE_INIT string @@ -164,4 +211,4 @@ config STONEYRIDGE_UART to FEDC_6FFFh. UART controller 1 registers range from FEDC_8000h to FEDC_8FFFh. -endif # SOC_AMD_STONEYRIDGE +endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 7c2682c9bd..9214488fc7 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -27,10 +27,19 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # #***************************************************************************** -ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) +ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) + +subdirs-y += ../../../cpu/amd/mtrr/ +subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/cache +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/pae +subdirs-y += ../../../cpu/x86/smm romstage-y += early_setup.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c +romstage-y += fixme.c romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c romstage-y += smbus.c romstage-y += smbus_spd.c @@ -39,12 +48,14 @@ romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c ramstage-y += chip.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c +ramstage-y += fixme.c ramstage-y += gpio.c ramstage-y += hda.c ramstage-y += hudson.c ramstage-y += ide.c ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c ramstage-y += lpc.c +ramstage-y += model_15_init.c ramstage-y += pci.c ramstage-y += pcie.c ramstage-y += reset.c @@ -233,4 +244,4 @@ apu/amdfw-type := raw endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -endif +endif # ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl new file mode 100644 index 0000000000..aae3287ba6 --- /dev/null +++ b/src/soc/amd/stoneyridge/acpi/cpu.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Processor Object + * + */ +Scope (\_PR) { /* define processor scope */ + Processor( + P000, /* name space name */ + 0, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + + Processor( + P001, /* name space name */ + 1, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P002, /* name space name */ + 2, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P003, /* name space name */ + 3, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P004, /* name space name */ + 4, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P005, /* name space name */ + 5, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P006, /* name space name */ + 6, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P007, /* name space name */ + 7, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } +} /* End _PR scope */ diff --git a/src/soc/amd/stoneyridge/fixme.c b/src/soc/amd/stoneyridge/fixme.c new file mode 100644 index 0000000000..781d0097b0 --- /dev/null +++ b/src/soc/amd/stoneyridge/fixme.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void amd_initcpuio(void) +{ + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of SB800 + * legacy devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and + * ACPI) are set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); + /* last address before processor local APIC at FEE00000 */ + PciData = 0x00FEDF00; + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); + /* lowest NP address is HPET at FED00000 */ + PciData = (0xFED00000 >> 8) | 3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); +} + +void amd_initmmio(void) +{ + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO + configuration base Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | \ + (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); + + /* For serial port */ + PciData = 0xFF03FFD5; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; + LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | \ + 0x800ull; + LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + + if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){ + LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); + MsrReg |= 1 << 11; + LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); + } +} diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c new file mode 100644 index 0000000000..02e5b79e84 --- /dev/null +++ b/src/soc/amd/stoneyridge/model_15_init.c @@ -0,0 +1,135 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +void PSPProgBar3Msr(void *Buffer); + +void PSPProgBar3Msr(void *Buffer) +{ + u32 Bar3Addr; + u64 Tmp64; + /* Get Bar3 Addr */ + Bar3Addr = PspLibPciReadPspConfig(0x20); + Tmp64 = Bar3Addr; + printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64); + LibAmdMsrWrite(0xC00110A2, &Tmp64, NULL); + LibAmdMsrRead(0xC00110A2, &Tmp64, NULL); +} + +static void model_15_init(device_t dev) +{ + printk(BIOS_DEBUG, "Model 15 Init.\n"); + + u8 i; + msr_t msr; + int msrno; +#if CONFIG_LOGICAL_CPUS + u32 siblings; +#endif + + disable_cache(); + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + // BSP: make a0000-bffff UC, c0000-fffff WB + msr.lo = msr.hi = 0; + wrmsr(0x259, msr); + msr.lo = msr.hi = 0x1e1e1e1e; + wrmsr(0x250, msr); + wrmsr(0x258, msr); + for (msrno = 0x268; msrno <= 0x26f; msrno++) + wrmsr(msrno, msr); + + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + x86_mtrr_check(); + x86_enable_cache(); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) + wrmsr(MCI_STATUS + (i * 4), msr); + + + /* Enable the local CPU APICs */ + setup_lapic(); + +#if CONFIG_LOGICAL_CPUS + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); +#endif + PSPProgBar3Msr(NULL); + + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + + + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); +} + +static struct device_operations cpu_dev_ops = { + .init = model_15_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x670f00 }, + { 0, 0 }, +}; + +static const struct cpu_driver model_15 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; -- cgit v1.2.3