From 16745e39b636ad58e0f43b254ceb7812b7fbe7f9 Mon Sep 17 00:00:00 2001
From: Marshall Dawson <marshalldawson3rd@gmail.com>
Date: Wed, 27 Sep 2017 14:53:34 -0600
Subject: amd/stoneyridge: Add pm_read32 and pm_write32 to southbridge

Duplicate existing pm_read and pm_write and create 32-bit register
access functions.

Change-Id: I916130a229dc7cef8dae1faf00a38501d3939979
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21749
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
---
 src/soc/amd/stoneyridge/southbridge.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'src/soc/amd/stoneyridge/southbridge.c')

diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index ebda770be2..8377eca9b0 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -58,6 +58,16 @@ u16 pm_read16(u8 reg)
 	return read16((void *)(PM_MMIO_BASE + reg));
 }
 
+void pm_write32(u8 reg, u32 value)
+{
+	write32((void *)(PM_MMIO_BASE + reg), value);
+}
+
+u32 pm_read32(u8 reg)
+{
+	return read32((void *)(PM_MMIO_BASE + reg));
+}
+
 void sb_enable(device_t dev)
 {
 	printk(BIOS_DEBUG, "%s\n", __func__);
-- 
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