From 7654f86f3ab5ad87b7a224b075842a35b8b8748b Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Fri, 1 Dec 2017 17:17:43 -0700 Subject: soc/amd/stoneyridge: Add XHCI PM register access functions Add functions to access the XHCI PM MMIO registers. Change-Id: I81b4c0a448eb17c5ee0562a2c3548a074d533a98 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/22677 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Marshall Dawson --- src/soc/amd/stoneyridge/sb_util.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'src/soc/amd/stoneyridge/sb_util.c') diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index f7c6b45ac3..8862b1710b 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -84,3 +84,33 @@ uint16_t pm_acpi_pm_evt_blk(void) { return pm_read16(PM_EVT_BLK); } + +void xhci_pm_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value); +} + +uint8_t xhci_pm_read8(uint8_t reg) +{ + return read8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg)); +} + +void xhci_pm_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value); +} + +uint16_t xhci_pm_read16(uint8_t reg) +{ + return read16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg)); +} + +void xhci_pm_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value); +} + +uint32_t xhci_pm_read32(uint8_t reg) +{ + return read32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg)); +} -- cgit v1.2.3