From 873b4e70bc4c829307864f6819490840e07b6660 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Tue, 12 Jun 2018 10:53:55 -0600 Subject: stoneyridge: Move agesa out of bootblock This is Garrett's patch with a bit of cleanup. BUG=b:65442212 TEST=Was able to boot, suspend and resume on grunt. Change-Id: I55959b59a4e60b679d959ebd77de27e5d454f5f7 Signed-off-by: Raul E Rangel Reviewed-on: https://review.coreboot.org/26478 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/stoneyridge/romstage.c | 44 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'src/soc/amd/stoneyridge/romstage.c') diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index a742cd062d..78472d332a 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -41,6 +41,44 @@ void __weak mainboard_romstage_entry(int s3_resume) /* By default, don't do anything */ } +static void load_smu_fw1(void) +{ + u32 base, limit, cmd; + + /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ + base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE; + limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); + pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit); + pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base); + + /* Preload a value into "BAR3" and enable it */ + pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE); + pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); + + /* Enable memory access and master */ + cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); + cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); + + psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw"); +} + +static void agesa_call(void) +{ + post_code(0x37); + do_agesawrapper(agesawrapper_amdinitreset, "amdinitreset"); + + post_code(0x38); + /* APs will not exit amdinitearly */ + do_agesawrapper(agesawrapper_amdinitearly, "amdinitearly"); +} + +static void bsp_agesa_call(void) +{ + set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */ + agesa_call(); +} + asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -61,6 +99,12 @@ asmlinkage void car_stage_entry(void) console_init(); + if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW)) + load_smu_fw1(); + + + bsp_agesa_call(); + mainboard_romstage_entry(s3_resume); if (!s3_resume) { -- cgit v1.2.3