From 22f54c5a81bf387edcd7ea792bc1717c554054c6 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Wed, 29 Nov 2017 09:30:23 -0700 Subject: amd/stoneyridge: Add NV storage to ramtop The scratch registers in northbridge used for storing the top of cacheable memory are volatile. Use the BiosRam storage in the FCH instead. TEST=Suspend and resume Kahlee with complete S3 patch stack BUG=b:69614064 Change-Id: Ieb3cfd173c70bf899a6391d62d1df87b38485f30 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/22726 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/amd/stoneyridge/ramtop.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'src/soc/amd/stoneyridge/ramtop.c') diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 8268477a32..e676465ce7 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -22,20 +22,16 @@ #include #include #include - -#define CBMEM_TOP_SCRATCHPAD 0x78 +#include void backup_top_of_low_cacheable(uintptr_t ramtop) { - uint16_t top_cache = ramtop >> 16; - pci_write_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD, top_cache); + biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); } uintptr_t restore_top_of_low_cacheable(void) { - uint16_t top_cache; - top_cache = pci_read_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD); - return (top_cache << 16); + return biosram_read32(BIOSRAM_CBMEM_TOP); } void *cbmem_top(void) -- cgit v1.2.3