From 1587dc8a2b4ddfe110cd0239c6506a320cccac96 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 15 May 2017 18:55:11 -0600 Subject: soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/stoneyridge/ramtop.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 src/soc/amd/stoneyridge/ramtop.c (limited to 'src/soc/amd/stoneyridge/ramtop.c') diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c new file mode 100644 index 0000000000..8fa81c715a --- /dev/null +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include +#include +#include + +#define CBMEM_TOP_SCRATCHPAD 0x78 + +void backup_top_of_low_cacheable(uintptr_t ramtop) +{ + uint16_t top_cache = ramtop >> 16; + pci_write_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD, top_cache); +} + +uintptr_t restore_top_of_low_cacheable(void) +{ + uint16_t top_cache; + top_cache = pci_read_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD); + return (top_cache << 16); +} -- cgit v1.2.3