From ee04881360db7d551cfa49ca80b9b1c21a466439 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 29 Jan 2021 22:31:40 +0100 Subject: soc/amd/*/psp: move MSR_CU_CBBCFG to common and rename to MSR_PSP_ADDR TEST=Checked that the MSR is the same for Stoneyridge, Picasso and Cezanne. Signed-off-by: Felix Held Change-Id: Id15715ed1c17f4fc475985dcb1c31a83713ee65c Reviewed-on: https://review.coreboot.org/c/coreboot/+/50149 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Angel Pons --- src/soc/amd/stoneyridge/psp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/amd/stoneyridge/psp.c') diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c index c24b8be1df..a7fead73dc 100644 --- a/src/soc/amd/stoneyridge/psp.c +++ b/src/soc/amd/stoneyridge/psp.c @@ -44,9 +44,9 @@ void *soc_get_mbox_address(void) /* Determine if Bar3Hide has been set, and if hidden get the base from * the MSR instead. */ if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) { - psp_mmio = rdmsr(MSR_CU_CBBCFG).lo; + psp_mmio = rdmsr(MSR_PSP_ADDR).lo; if (psp_mmio == 0xffffffff) { - printk(BIOS_WARNING, "PSP: BAR hidden, MSR val uninitialized\n"); + printk(BIOS_WARNING, "PSP: BAR hidden, MSR_PSP_ADDR uninitialized\n"); return 0; } } else { -- cgit v1.2.3