From b30d0545843b6ba3e8c0976a1fc0f1413be1608b Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 09:42:47 +0200 Subject: soc/amd/stoneyridge: Fix 16-bit read/write PCI_COMMAND register Change-Id: I7b39e895501c3bc672a9dffec06b7969dc2f911f Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40789 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/stoneyridge/psp.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/soc/amd/stoneyridge/psp.c') diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c index 88bd61d4dd..5a4cd4dbab 100644 --- a/src/soc/amd/stoneyridge/psp.c +++ b/src/soc/amd/stoneyridge/psp.c @@ -12,7 +12,8 @@ void soc_enable_psp_early(void) { - u32 base, limit, cmd; + u32 base, limit; + u16 cmd; /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE; @@ -25,9 +26,9 @@ void soc_enable_psp_early(void) pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); /* Enable memory access and master */ - cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); + cmd = pci_read_config16(SOC_PSP_DEV, PCI_COMMAND); cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; - pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); + pci_write_config16(SOC_PSP_DEV, PCI_COMMAND, cmd); }; void *soc_get_mbox_address(void) -- cgit v1.2.3