From b617211910e9c6ff4e3cd92f022ef052a65559a3 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Wed, 13 Sep 2017 17:47:31 -0600 Subject: amd/stoneyridge: Enable SMM in TSEG MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add necessary features to allow mp_init_with_smm() to install and relocate an SMM handler. SMM region functions are added to easily identify the SMM attributes. Adjust the neighboring cbmem_top() rounding downward to better reflect the default TSEG size. Add relocation attributes to be set by each core a relocation handler. Modify the definition of smi_southbridge_handler() to match TSEG prototype. BUG=b:62103112 Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/21501 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Kyösti Mälkki --- src/soc/amd/stoneyridge/northbridge.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/soc/amd/stoneyridge/northbridge.c') diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 11fb336058..7ae252f33c 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -415,6 +415,8 @@ void domain_set_resources(device_t dev) u32 hole; int idx; struct bus *link; + void *tseg_base; + size_t tseg_size; pci_tolm = 0xffffffffUL; for (link = dev->link_list ; link ; link = link->next) @@ -505,6 +507,12 @@ void domain_set_resources(device_t dev) */ mmio_resource(dev, 0xa0000, 0xa0000 / KiB, 0x20000 / KiB); reserved_ram_resource(dev, 0xc0000, 0xc0000 / KiB, 0x40000 / KiB); + + /* Reserve TSEG */ + smm_region_info(&tseg_base, &tseg_size); + idx += 0x10; + reserved_ram_resource(dev, idx, (unsigned long)tseg_base/KiB, + tseg_size/KiB); } /********************************************************************* -- cgit v1.2.3