From bbcfa8afd59b4e31a6ef820e133b3f7353c45b2a Mon Sep 17 00:00:00 2001 From: Richard Spiegel Date: Thu, 12 Apr 2018 10:22:31 -0700 Subject: soc/amd/stoneyridge/lpc.c: Fix bit definitions The latest public BKDG (3.6) releases some previously undefined (reserved) bits, also some bits were wrongly named (possibly copied from previous chip). Fix these definitions, including the header file where they are defined. BUG=b:77940747 TEST=Build and boot grunt. Change-Id: Ie8d3fcccb8443c1a6db828bdc2624778bad6ba9f Signed-off-by: Richard Spiegel Reviewed-on: https://review.coreboot.org/25658 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Paul Menzel --- src/soc/amd/stoneyridge/lpc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/soc/amd/stoneyridge/lpc.c') diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index 10f4a4b7df..eb512817b6 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -76,11 +76,12 @@ static void lpc_init(device_t dev) pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte); /* - * bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. - * todo: verify against BKDG + * IMC is not used, but some of its registers and ports need to be + * programmed/accessed. So enable CPU access to them. This fixes + * SPI_CS# timing issue when running at 66MHz. */ byte = pci_read_config8(dev, LPC_HOST_CONTROL); - byte |= SPI_FROM_HOST_PREFETCH_EN | 1 << 3; + byte |= IMC_PAGE_FROM_HOST_EN | IMC_PORT_FROM_HOST_EN; pci_write_config8(dev, LPC_HOST_CONTROL, byte); cmos_check_update_date(); -- cgit v1.2.3