From eceaa97b27b04a61dd5fb2e68e0f5ac1367a3c0f Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Sun, 5 May 2019 18:35:12 -0600 Subject: soc/amd/stoneyridge: Rework SPI base address get/set A subsequent patch will move the soc//stoneyridge LPC functionality to a common directory. Prepare by reworking the SPI BAR configuration function in southbridge.h. The SPI BAR is not a typical PCI BAR, and is at D14F3xA0. Change-Id: I73ddb4afaf9e67ca0522ecb6085b23c92fedc461 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/32652 Reviewed-by: Martin Roth Reviewed-by: Richard Spiegel Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/include/soc/southbridge.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/soc/amd/stoneyridge/include') diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 6734efb04d..0ac43857e5 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -357,12 +357,11 @@ #define LPC_WIDEIO2_GENERIC_PORT 0x90 #define SPIROM_BASE_ADDRESS_REGISTER 0xa0 -#define SPI_BASE_RESERVED (BIT(4) | BIT(5)) +#define SPI_BASE_ALIGNMENT BIT(6) #define ROUTE_TPM_2_SPI BIT(3) #define SPI_ABORT_ENABLE BIT(2) #define SPI_ROM_ENABLE BIT(1) #define SPI_ROM_ALT_ENABLE BIT(0) -#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) /* LPC register 0xb8 is DWORD, here there are definitions for byte access. For example, bits 31-24 are accessed through byte access -- cgit v1.2.3