From e8e72bd0ca3ea84ba21db4318589e5c903085419 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Wed, 4 Oct 2017 22:12:31 -0600 Subject: stoneyridge: Add SCI/GPE configuration Add functions for configuring the GPE ACPI SCI events. BUG=b:63268311 BRANCH=none TEST=With the Kahlee GPE setup patch, test lidswitch powers the device on and off at the login screen. Change-Id: I5c282268edbd7b92a3f2ca7c72896406c8f8512f Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/22095 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/amd/stoneyridge/include/soc/smi.h | 38 +++++++++++++++++++++-- src/soc/amd/stoneyridge/include/soc/southbridge.h | 2 ++ 2 files changed, 37 insertions(+), 3 deletions(-) (limited to 'src/soc/amd/stoneyridge/include') diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 797f4e8578..34d3d74848 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -20,7 +20,18 @@ #include +#define SMI_GEVENTS 24 +#define SCIMAPS 58 +#define SCI_GPES 32 + +#define SMI_EVENT_STATUS 0x0 +#define SMI_EVENT_ENABLE 0x04 +#define SMI_SCI_TRIG 0x08 +#define SMI_SCI_LEVEL 0x0c #define SMI_SCI_STATUS 0x10 +#define SMI_SCI_EN 0x14 +#define SMI_SCI_MAP0 0x40 +# define SMI_SCI_MAP(X) (SMI_SCI_MAP0 + (X)) /* SMI source and status */ #define SMITYPE_AGPIO65 0 @@ -189,9 +200,21 @@ enum smi_mode { SMI_MODE_IRQ13 = 3, }; -enum smi_lvl { - SMI_LVL_LOW = 0, - SMI_LVL_HIGH = 1, +enum smi_sci_type { + NONE, + SCI, + SMI, + BOTH, +}; + +enum smi_sci_lvl { + SMI_SCI_LVL_LOW, + SMI_SCI_LVL_HIGH, +}; + +enum smi_sci_dir { + SMI_SCI_EDG, + SMI_SCI_LVL, }; struct smi_sources_t { @@ -199,10 +222,19 @@ struct smi_sources_t { void (*handler)(void); }; +struct sci_source { + uint8_t scimap; /* SCIMAP 0-57 */ + uint8_t gpe; /* 32 GPEs */ + uint8_t direction; /* Active High or Low, smi_sci_lvl */ + uint8_t level; /* Edge or Level, smi_sci_dir */ +}; + uint16_t pm_acpi_smi_cmd_port(void); void configure_smi(uint8_t smi_num, uint8_t mode); void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); +void configure_scimap(const struct sci_source *sci); void disable_gevent_smi(uint8_t gevent); +void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); #ifndef __SMM__ void enable_smi_generation(void); diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 8e04b68ab2..55ded9ffa8 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -276,8 +276,10 @@ u32 pm_read32(u8 reg); void pm_write8(u8 reg, u8 value); void pm_write16(u8 reg, u16 value); void pm_write32(u8 reg, u32 value); +u8 smi_read8(u8 reg); u16 smi_read16(u8 reg); u32 smi_read32(u8 reg); +void smi_write8(u8 reg, u8 value); void smi_write16(u8 reg, u16 value); void smi_write32(u8 reg, u32 value); uint16_t pm_acpi_pm_cnt_blk(void); -- cgit v1.2.3