From dfeb1c4da9be7ac97bd31f580ff2fff0c4b3256e Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 7 Aug 2017 19:08:24 -0600 Subject: stoneyridge: Rename hudson to southbridge Simplify funciton names and remove reference to hudson in stoneyridge. The southbridge in Stoney Ridge is Kern and hudson naming is no longer accurate. BUG=b:62200157 BRANCH=none TEST=Build and booted on Kahlee. Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/20912 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/include/soc/hudson.h | 209 ---------------------- src/soc/amd/stoneyridge/include/soc/smi.h | 8 +- src/soc/amd/stoneyridge/include/soc/southbridge.h | 207 +++++++++++++++++++++ 3 files changed, 211 insertions(+), 213 deletions(-) delete mode 100644 src/soc/amd/stoneyridge/include/soc/hudson.h create mode 100644 src/soc/amd/stoneyridge/include/soc/southbridge.h (limited to 'src/soc/amd/stoneyridge/include') diff --git a/src/soc/amd/stoneyridge/include/soc/hudson.h b/src/soc/amd/stoneyridge/include/soc/hudson.h deleted file mode 100644 index 48f5e0d937..0000000000 --- a/src/soc/amd/stoneyridge/include/soc/hudson.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef STONEYRIDGE_H -#define STONEYRIDGE_H - -#include -#include -#include -#include -#include "chip.h" - -#define IO_APIC2_ADDR 0xfec20000 - -/* Offsets from ACPI_MMIO_BASE - * This is defined by AGESA, but we don't include AGESA headers to avoid - * polluting the namespace. - */ -#define PM_MMIO_BASE 0xfed80300 - -#define APU_UART0_BASE 0xfedc6000 -#define APU_UART1_BASE 0xfedc8000 - -/* Power management index/data registers */ -#define BIOSRAM_INDEX 0xcd4 -#define BIOSRAM_DATA 0xcd5 -#define PM_INDEX 0xcd6 -#define PM_DATA 0xcd7 -#define PM2_INDEX 0xcd0 -#define PM2_DATA 0xcd1 - -#define PM_ACPI_MMIO_EN 0x24 -#define PM_SERIRQ_CONF 0x54 -#define PM_EVT_BLK 0x60 -#define PM1_CNT_BLK 0x62 -#define PM_TMR_BLK 0x64 -#define PM_CPU_CTRL 0x66 -#define PM_GPE0_BLK 0x68 -#define PM_ACPI_SMI_CMD 0x6a -#define PM_ACPI_CONF 0x74 -#define PM_PMIO_DEBUG 0xd2 -#define PM_MANUAL_RESET 0xd3 -#define PM_HUD_SD_FLASH_CTRL 0xe7 -#define PM_YANG_SD_FLASH_CTRL 0xe8 -#define PM_PCIB_CFG 0xea - -#define SYS_RESET 0xcf9 - -#define STONEYRIDGE_ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE -#define ACPI_PM_EVT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */ -#define ACPI_PM1_CNT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */ -#define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */ -#define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */ -#define ACPI_CPU_CONTROL (STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */ - -#define ACPI_SMI_CTL_PORT 0xb2 -#define ACPI_SMI_CMD_CST_CONTROL 0xde -#define ACPI_SMI_CMD_PST_CONTROL 0xad -#define ACPI_SMI_CMD_DISABLE 0xbe -#define ACPI_SMI_CMD_ENABLE 0xef -#define ACPI_SMI_CMD_S4_REQ 0xc0 - -#define REV_STONEYRIDGE_A11 0x11 -#define REV_STONEYRIDGE_A12 0x12 - -#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 -#define ROUTE_TPM_2_SPI BIT(3) -#define SPI_ROM_ENABLE 0x02 -#define SPI_BASE_ADDRESS 0xfec10000 - -#define LPC_IO_PORT_DECODE_ENABLE 0x44 -#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) -#define DECODE_ENABLE_PARALLEL_PORT1 BIT(1) -#define DECODE_ENABLE_PARALLEL_PORT2 BIT(2) -#define DECODE_ENABLE_PARALLEL_PORT3 BIT(3) -#define DECODE_ENABLE_PARALLEL_PORT4 BIT(4) -#define DECODE_ENABLE_PARALLEL_PORT5 BIT(5) -#define DECODE_ENABLE_SERIAL_PORT0 BIT(6) -#define DECODE_ENABLE_SERIAL_PORT1 BIT(7) -#define DECODE_ENABLE_SERIAL_PORT2 BIT(8) -#define DECODE_ENABLE_SERIAL_PORT3 BIT(9) -#define DECODE_ENABLE_SERIAL_PORT4 BIT(10) -#define DECODE_ENABLE_SERIAL_PORT5 BIT(11) -#define DECODE_ENABLE_SERIAL_PORT6 BIT(12) -#define DECODE_ENABLE_SERIAL_PORT7 BIT(13) -#define DECODE_ENABLE_AUDIO_PORT0 BIT(14) -#define DECODE_ENABLE_AUDIO_PORT1 BIT(15) -#define DECODE_ENABLE_AUDIO_PORT2 BIT(16) -#define DECODE_ENABLE_AUDIO_PORT3 BIT(17) -#define DECODE_ENABLE_MIDI_PORT0 BIT(18) -#define DECODE_ENABLE_MIDI_PORT1 BIT(19) -#define DECODE_ENABLE_MIDI_PORT2 BIT(20) -#define DECODE_ENABLE_MIDI_PORT3 BIT(21) -#define DECODE_ENABLE_MSS_PORT0 BIT(22) -#define DECODE_ENABLE_MSS_PORT1 BIT(23) -#define DECODE_ENABLE_MSS_PORT2 BIT(24) -#define DECODE_ENABLE_MSS_PORT3 BIT(25) -#define DECODE_ENABLE_FDC_PORT0 BIT(26) -#define DECODE_ENABLE_FDC_PORT1 BIT(27) -#define DECODE_ENABLE_GAME_PORT BIT(28) -#define DECODE_ENABLE_KBC_PORT BIT(29) -#define DECODE_ENABLE_ACPIUC_PORT BIT(30) -#define DECODE_ENABLE_ADLIB_PORT BIT(31) - -#define LPC_IO_OR_MEM_DECODE_ENABLE 0x48 -#define LPC_WIDEIO2_ENABLE BIT(25) -#define LPC_WIDEIO1_ENABLE BIT(24) -#define LPC_WIDEIO0_ENABLE BIT(2) - -#define LPC_WIDEIO_GENERIC_PORT 0x64 - -#define LPC_ALT_WIDEIO_RANGE_ENABLE 0x74 -#define LPC_ALT_WIDEIO2_ENABLE BIT(3) -#define LPC_ALT_WIDEIO1_ENABLE BIT(2) -#define LPC_ALT_WIDEIO0_ENABLE BIT(0) - -#define LPC_WIDEIO2_GENERIC_PORT 0x90 - -#define SPI_CNTRL0 0x00 -#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) -/* Nominal is 16.7MHz on older devices, 33MHz on newer */ -#define SPI_READ_MODE_NOM 0x00000000 -#define SPI_READ_MODE_DUAL112 ( BIT(29) ) -#define SPI_READ_MODE_QUAD114 ( BIT(29) | BIT(18)) -#define SPI_READ_MODE_DUAL122 (BIT(30) ) -#define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18)) -#define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) ) -/* Nominal and SPI_READ_MODE_FAST_HUDSON1 are the only valid choices for H1 */ -#define SPI_READ_MODE_FAST_HUDSON1 ( BIT(18)) -#define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18)) -#define SPI_ARB_ENABLE BIT(19) - -#define SPI_CNTRL1 0x0c -/* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */ -#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) -#define SPI_NORM_SPEED_SH 12 -#define SPI_FAST_SPEED_SH 8 - -#define SPI100_ENABLE 0x20 -#define SPI_USE_SPI100 BIT(0) - -#define SPI100_SPEED_CONFIG 0x22 -#define SPI_SPEED_66M (0x0) -#define SPI_SPEED_33M ( BIT(0)) -#define SPI_SPEED_22M ( BIT(1) ) -#define SPI_SPEED_16M ( BIT(1) | BIT(0)) -#define SPI_SPEED_100M (BIT(2) ) -#define SPI_SPEED_800K (BIT(2) | BIT(0)) -#define SPI_NORM_SPEED_NEW_SH 12 -#define SPI_FAST_SPEED_NEW_SH 8 -#define SPI_ALT_SPEED_NEW_SH 4 -#define SPI_TPM_SPEED_NEW_SH 0 - -#define SPI100_HOST_PREF_CONFIG 0x2c -#define SPI_RD4DW_EN_HOST BIT(15) - -static inline int hudson_sata_enable(void) -{ - /* True if IDE or AHCI. */ - return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || - (CONFIG_STONEYRIDGE_SATA_MODE == 2); -} - -static inline int hudson_ide_enable(void) -{ - /* True if IDE or LEGACY IDE. */ - return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || - (CONFIG_STONEYRIDGE_SATA_MODE == 3); -} - -void hudson_enable_rom(void); -void configure_hudson_uart(void); -void hudson_clk_output_48Mhz(void); -void hudson_disable_4dw_burst(void); -void hudson_enable(device_t dev); -void hudson_final(void *chip_info); -void hudson_init(void *chip_info); -void hudson_lpc_port80(void); -void hudson_lpc_decode(void); -void hudson_pci_port80(void); -void hudson_read_mode(u32 mode); -void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); -void hudson_set_readspeed(u16 norm, u16 fast); -void hudson_tpm_decode_spi(void); -void lpc_wideio_512_window(uint16_t base); -void lpc_wideio_16_window(uint16_t base); -u8 pm_read8(u8 reg); -u16 pm_read16(u16 reg); -void pm_write8(u8 reg, u8 value); -void pm_write16(u8 reg, u16 value); -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); -void s3_resume_init_data(void *FchParams); -int s3_save_nvram_early(u32 dword, int size, int nvram_pos); -void bootblock_fch_early_init(void); - -#endif /* STONEYRIDGE_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 7a3c804452..193fb0ced3 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -54,12 +54,12 @@ static inline void smi_write16(uint8_t offset, uint16_t value) write16((void *)(SMI_BASE + offset), value); } -void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); -void hudson_disable_gevent_smi(uint8_t gevent); -void hudson_enable_acpi_cmd_smi(void); +void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); +void disable_gevent_smi(uint8_t gevent); +void enable_acpi_cmd_smi(void); #ifndef __SMM__ -void hudson_enable_smi_generation(void); +void enable_smi_generation(void); #endif #endif /* _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h new file mode 100644 index 0000000000..de481f0eea --- /dev/null +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -0,0 +1,207 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef STONEYRIDGE_H +#define STONEYRIDGE_H + +#include +#include +#include +#include +#include "chip.h" + +#define IO_APIC2_ADDR 0xfec20000 + +/* Offsets from ACPI_MMIO_BASE + * This is defined by AGESA, but we don't include AGESA headers to avoid + * polluting the namespace. + */ +#define PM_MMIO_BASE 0xfed80300 + +#define APU_UART0_BASE 0xfedc6000 +#define APU_UART1_BASE 0xfedc8000 + +/* Power management index/data registers */ +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 +#define PM_INDEX 0xcd6 +#define PM_DATA 0xcd7 +#define PM2_INDEX 0xcd0 +#define PM2_DATA 0xcd1 + +#define PM_ACPI_MMIO_EN 0x24 +#define PM_SERIRQ_CONF 0x54 +#define PM_EVT_BLK 0x60 +#define PM1_CNT_BLK 0x62 +#define PM_TMR_BLK 0x64 +#define PM_CPU_CTRL 0x66 +#define PM_GPE0_BLK 0x68 +#define PM_ACPI_SMI_CMD 0x6a +#define PM_ACPI_CONF 0x74 +#define PM_PMIO_DEBUG 0xd2 +#define PM_MANUAL_RESET 0xd3 +#define PM_HUD_SD_FLASH_CTRL 0xe7 +#define PM_YANG_SD_FLASH_CTRL 0xe8 +#define PM_PCIB_CFG 0xea + +#define SYS_RESET 0xcf9 + +#define STONEYRIDGE_ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE +#define ACPI_PM_EVT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */ +#define ACPI_PM1_CNT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */ +#define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */ +#define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */ +#define ACPI_CPU_CONTROL (STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */ + +#define ACPI_SMI_CTL_PORT 0xb2 +#define ACPI_SMI_CMD_CST_CONTROL 0xde +#define ACPI_SMI_CMD_PST_CONTROL 0xad +#define ACPI_SMI_CMD_DISABLE 0xbe +#define ACPI_SMI_CMD_ENABLE 0xef +#define ACPI_SMI_CMD_S4_REQ 0xc0 + +#define REV_STONEYRIDGE_A11 0x11 +#define REV_STONEYRIDGE_A12 0x12 + +#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define ROUTE_TPM_2_SPI BIT(3) +#define SPI_ROM_ENABLE 0x02 +#define SPI_BASE_ADDRESS 0xfec10000 + +#define LPC_IO_PORT_DECODE_ENABLE 0x44 +#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) +#define DECODE_ENABLE_PARALLEL_PORT1 BIT(1) +#define DECODE_ENABLE_PARALLEL_PORT2 BIT(2) +#define DECODE_ENABLE_PARALLEL_PORT3 BIT(3) +#define DECODE_ENABLE_PARALLEL_PORT4 BIT(4) +#define DECODE_ENABLE_PARALLEL_PORT5 BIT(5) +#define DECODE_ENABLE_SERIAL_PORT0 BIT(6) +#define DECODE_ENABLE_SERIAL_PORT1 BIT(7) +#define DECODE_ENABLE_SERIAL_PORT2 BIT(8) +#define DECODE_ENABLE_SERIAL_PORT3 BIT(9) +#define DECODE_ENABLE_SERIAL_PORT4 BIT(10) +#define DECODE_ENABLE_SERIAL_PORT5 BIT(11) +#define DECODE_ENABLE_SERIAL_PORT6 BIT(12) +#define DECODE_ENABLE_SERIAL_PORT7 BIT(13) +#define DECODE_ENABLE_AUDIO_PORT0 BIT(14) +#define DECODE_ENABLE_AUDIO_PORT1 BIT(15) +#define DECODE_ENABLE_AUDIO_PORT2 BIT(16) +#define DECODE_ENABLE_AUDIO_PORT3 BIT(17) +#define DECODE_ENABLE_MIDI_PORT0 BIT(18) +#define DECODE_ENABLE_MIDI_PORT1 BIT(19) +#define DECODE_ENABLE_MIDI_PORT2 BIT(20) +#define DECODE_ENABLE_MIDI_PORT3 BIT(21) +#define DECODE_ENABLE_MSS_PORT0 BIT(22) +#define DECODE_ENABLE_MSS_PORT1 BIT(23) +#define DECODE_ENABLE_MSS_PORT2 BIT(24) +#define DECODE_ENABLE_MSS_PORT3 BIT(25) +#define DECODE_ENABLE_FDC_PORT0 BIT(26) +#define DECODE_ENABLE_FDC_PORT1 BIT(27) +#define DECODE_ENABLE_GAME_PORT BIT(28) +#define DECODE_ENABLE_KBC_PORT BIT(29) +#define DECODE_ENABLE_ACPIUC_PORT BIT(30) +#define DECODE_ENABLE_ADLIB_PORT BIT(31) + +#define LPC_IO_OR_MEM_DECODE_ENABLE 0x48 +#define LPC_WIDEIO2_ENABLE BIT(25) +#define LPC_WIDEIO1_ENABLE BIT(24) +#define LPC_WIDEIO0_ENABLE BIT(2) + +#define LPC_WIDEIO_GENERIC_PORT 0x64 + +#define LPC_ALT_WIDEIO_RANGE_ENABLE 0x74 +#define LPC_ALT_WIDEIO2_ENABLE BIT(3) +#define LPC_ALT_WIDEIO1_ENABLE BIT(2) +#define LPC_ALT_WIDEIO0_ENABLE BIT(0) + +#define LPC_WIDEIO2_GENERIC_PORT 0x90 + +#define SPI_CNTRL0 0x00 +#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) +/* Nominal is 16.7MHz on older devices, 33MHz on newer */ +#define SPI_READ_MODE_NOM 0x00000000 +#define SPI_READ_MODE_DUAL112 ( BIT(29) ) +#define SPI_READ_MODE_QUAD114 ( BIT(29) | BIT(18)) +#define SPI_READ_MODE_DUAL122 (BIT(30) ) +#define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18)) +#define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) ) +#define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18)) +#define SPI_ARB_ENABLE BIT(19) + +#define SPI_CNTRL1 0x0c +/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ +#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) +#define SPI_NORM_SPEED_SH 12 +#define SPI_FAST_SPEED_SH 8 + +#define SPI100_ENABLE 0x20 +#define SPI_USE_SPI100 BIT(0) + +#define SPI100_SPEED_CONFIG 0x22 +#define SPI_SPEED_66M (0x0) +#define SPI_SPEED_33M ( BIT(0)) +#define SPI_SPEED_22M ( BIT(1) ) +#define SPI_SPEED_16M ( BIT(1) | BIT(0)) +#define SPI_SPEED_100M (BIT(2) ) +#define SPI_SPEED_800K (BIT(2) | BIT(0)) +#define SPI_NORM_SPEED_NEW_SH 12 +#define SPI_FAST_SPEED_NEW_SH 8 +#define SPI_ALT_SPEED_NEW_SH 4 +#define SPI_TPM_SPEED_NEW_SH 0 + +#define SPI100_HOST_PREF_CONFIG 0x2c +#define SPI_RD4DW_EN_HOST BIT(15) + +static inline int sb_sata_enable(void) +{ + /* True if IDE or AHCI. */ + return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || + (CONFIG_STONEYRIDGE_SATA_MODE == 2); +} + +static inline int sb_ide_enable(void) +{ + /* True if IDE or LEGACY IDE. */ + return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || + (CONFIG_STONEYRIDGE_SATA_MODE == 3); +} + +void sb_enable_rom(void); +void configure_stoneyridge_uart(void); +void sb_clk_output_48Mhz(void); +void sb_disable_4dw_burst(void); +void sb_enable(device_t dev); +void southbridge_final(void *chip_info); +void southbridge_init(void *chip_info); +void sb_lpc_port80(void); +void sb_lpc_decode(void); +void sb_pci_port80(void); +void sb_read_mode(u32 mode); +void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); +void sb_set_readspeed(u16 norm, u16 fast); +void sb_tpm_decode_spi(void); +void lpc_wideio_512_window(uint16_t base); +void lpc_wideio_16_window(uint16_t base); +u8 pm_read8(u8 reg); +u16 pm_read16(u16 reg); +void pm_write8(u8 reg, u8 value); +void pm_write16(u8 reg, u16 value); +int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); +void s3_resume_init_data(void *FchParams); +int s3_save_nvram_early(u32 dword, int size, int nvram_pos); +void bootblock_fch_early_init(void); + +#endif /* STONEYRIDGE_H */ -- cgit v1.2.3