From d85c4afea56b3ca0eca4de3707884802bbdcca45 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Wed, 28 Mar 2018 19:48:42 -0600 Subject: amd/stoneyridge: Use defined value for SPI flash MTRR Replace an absolute value with a #define value in bootblock. This is in preparation for using an additional MTRR in a subsequent patch. Change-Id: I006c7cfa0057b3ed4a21359fc8367caf6ec5baf3 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/25455 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/soc/amd/stoneyridge/include/soc/cpu.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src/soc/amd/stoneyridge/include') diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h index d2c412f4ef..bf8ed496ef 100644 --- a/src/soc/amd/stoneyridge/include/soc/cpu.h +++ b/src/soc/amd/stoneyridge/include/soc/cpu.h @@ -16,6 +16,17 @@ #ifndef __STONEYRIDGE_CPU_H__ #define __STONEYRIDGE_CPU_H__ +#include + +/* + * Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest + * numbered registers. Any values defined below are subtracted from the + * highest numbered registers. + * + * todo: Revisit this once AGESA no longer programs MTRRs. + */ +#define SOC_EARLY_VMTRR_FLASH 2 + void stoney_init_cpus(struct device *dev); #endif /* __STONEYRIDGE_CPU_H__ */ -- cgit v1.2.3