From d2558304183e3f79e2dfbfdab4c1b78f8f222217 Mon Sep 17 00:00:00 2001 From: Garrett Kirkendall Date: Tue, 6 Mar 2018 09:05:20 -0600 Subject: soc/amd/stoneyridge: clean up OSCOUT1_ClkOutputEnb Change OSCOUT1_ClkOutputEnb programming to use registers from iomap.h and southbridge.h BUG=b:69220826 BRANCH=master TEST=abuild, build Gardenia, build and boot Grunt Change-Id: Ib138dae6057394740c415e882e4dbd925882c2de Signed-off-by: Garrett Kirkendall Reviewed-on: https://review.coreboot.org/25009 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Richard Spiegel --- src/soc/amd/stoneyridge/include/soc/southbridge.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/soc/amd/stoneyridge/include') diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index b4c7089773..780a9e33d2 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -247,7 +247,8 @@ #define SPI100_HOST_PREF_CONFIG 0x2c #define SPI_RD4DW_EN_HOST BIT(15) -#define FCH_MISC_REG40_OSCOUT1_EN BIT(2) +#define MISC_MISC_CLK_CNTL_1 0x40 +#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ /* IO 0xcf9 - Reset control port*/ #define FULL_RST BIT(3) -- cgit v1.2.3