From 9df969aebfdeb6d162cd2aeb288fa4420a21953a Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 25 Jul 2017 18:46:46 -0600 Subject: soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK Add dedicated CAR setup and teardown functions and Kconfig options to force their inclusion into the build. The .S files are mostly duplicated code from the old cache_as_ram.inc file. The .S files use global proc names in anticipation for use with the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE. Move the mainboard romstage functionality into the soc directory and change the function name to be compatible with the call from assembly_entry.S. Drop the BIST check like other devices. Move InitReset and InitEarly to bootblock. These AGESA entry points set some default settings, and release/recapture the AP cores. There are currently some early dependencies on InitReset. Future work should include: * Pull the necessary functionality from InitReset into bootblock * Move InitReset and InitEarly to car_stage_entry() and out of bootblock - Add a mechanism for the BSP to give the APs an address to call and skip most of bootblock and verstage (when available) (1) - Reunify BiosCallOuts.c and OemCustomize.c (1) During the InitReset call, the BSP enables the APs by setting core enable bits in F18F0x1DC and APs begin fetching/executing from the reset vector. The BSP waits for all APs to also reach InitReset, where they enter an endless loop. The BSP sends a command to them to execute a HLT instruction and the BSP eventually returns from InitReset. The goal would be to preserve this process but prevent APs from rerunning early code. Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/19755 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Martin Roth --- src/soc/amd/stoneyridge/include/soc/hudson.h | 2 ++ src/soc/amd/stoneyridge/include/soc/northbridge.h | 4 ++++ 2 files changed, 6 insertions(+) (limited to 'src/soc/amd/stoneyridge/include') diff --git a/src/soc/amd/stoneyridge/include/soc/hudson.h b/src/soc/amd/stoneyridge/include/soc/hudson.h index c69ab679e6..62d5a84395 100644 --- a/src/soc/amd/stoneyridge/include/soc/hudson.h +++ b/src/soc/amd/stoneyridge/include/soc/hudson.h @@ -179,6 +179,7 @@ static inline int hudson_ide_enable(void) (CONFIG_STONEYRIDGE_SATA_MODE == 3); } +void hudson_enable_rom(void); void configure_hudson_uart(void); void hudson_clk_output_48Mhz(void); void hudson_disable_4dw_burst(void); @@ -201,5 +202,6 @@ void pm_write16(u8 reg, u16 value); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); void s3_resume_init_data(void *FchParams); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); +void bootblock_fch_early_init(void); #endif /* STONEYRIDGE_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index a87d66b845..e082a9d067 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -16,6 +16,7 @@ #ifndef PI_STONEYRIDGE_NORTHBRIDGE_H #define PI_STONEYRIDGE_NORTHBRIDGE_H +#include #include #include @@ -26,4 +27,7 @@ void domain_set_resources(device_t dev); void fam15_finalize(void *chip_info); void setup_uma_memory(void); +/* todo: remove this when postcar stage is in place */ +asmlinkage void chipset_teardown_car(void); + #endif /* PI_STONEYRIDGE_NORTHBRIDGE_H */ -- cgit v1.2.3