From 8f031d8234212266a6a18747415550ae5b89c776 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 9 Apr 2018 22:15:06 -0600 Subject: amd/stoneyridge: Reorder temp mtrr for flash Relocate setting the temp range MTRR, for the SPI flash device, to after completion of mp_init. The mp_init functionality mirrors the BSP's exact MTRR settings into the AP cores. The ranges need to be the correct calculated values and not some temporary setting. This solves an MTRR sync issue on APUs with more than two cores, i.e. more than a single compute-unit. MTRRs within a CU are shared so the AP always stays in sync. BUG=b:77457944 TEST=run on Kahlee Change-Id: Idc4cccdf721e252bc87d6cba62a3406a9f19b940 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/25575 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/amd/stoneyridge/cpu.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'src/soc/amd/stoneyridge/cpu.c') diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 14b6881a1a..15dd38147c 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -49,10 +49,6 @@ static struct smm_relocation_attrs relo_attrs; static void pre_mp_init(void) { x86_setup_mtrrs_with_detect(); - - /* The flash is now no longer cacheable. Reset to WP for performance. */ - mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); - x86_mtrr_check(); } @@ -113,6 +109,9 @@ void stoney_init_cpus(struct device *dev) /* Clear for take-off */ if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) printk(BIOS_ERR, "MP initialization failure.\n"); + + /* The flash is now no longer cacheable. Reset to WP for performance. */ + mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); } static void model_15_init(device_t dev) -- cgit v1.2.3