From 400ce55566caa541304b2483e61bcc2df941998c Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Fri, 12 Oct 2018 10:54:30 +0200
Subject: cpu/amd: Use common AMD's MSR

Phase 1. Due to the size of the effort, this CL is broken into several
phases.

Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
---
 src/soc/amd/stoneyridge/cpu.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/soc/amd/stoneyridge/cpu.c')

diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 92b2950ad3..c140fca7db 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -18,8 +18,8 @@
 #include <cpu/x86/mp.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
 #include <cpu/x86/lapic.h>
-#include <cpu/amd/amdfam15.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
 #include <soc/pci_devs.h>
@@ -89,10 +89,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase,
 
 	tseg_base.lo = relo_attrs.tseg_base;
 	tseg_base.hi = 0;
-	wrmsr(MSR_TSEG_BASE, tseg_base);
+	wrmsr(SMM_ADDR_MSR, tseg_base);
 	tseg_mask.lo = relo_attrs.tseg_mask;
 	tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1);
-	wrmsr(MSR_SMM_MASK, tseg_mask);
+	wrmsr(SMM_MASK_MSR, tseg_mask);
 	smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase);
 	smm_state->smbase = staggered_smbase;
 }
-- 
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