From 200d213d1bae614fcd35913c1d46fec7e495717f Mon Sep 17 00:00:00 2001 From: Michał Żygowski Date: Fri, 6 Dec 2019 12:07:52 +0100 Subject: amdblocks/pci: add common implementation of MMCONF enabling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add common function to enable PCI MMCONF base address. Use the common function in stoneyridge bootblock. Signed-off-by: Michał Żygowski Change-Id: I1bb8b22b282584c421a9fffa3322b2a8e406d037 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37552 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/amd/stoneyridge/bootblock/bootblock.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'src/soc/amd/stoneyridge/bootblock/bootblock.c') diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index d92535ac31..9920aff082 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -42,15 +43,9 @@ /* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */ static void amd_initmmio(void) { - msr_t mmconf; msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); int mtrr; - mmconf.hi = 0; - mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN - | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; - wrmsr(MMIO_CONF_BASE, mmconf); - /* * todo: AGESA currently writes variable MTRRs. Once that is * corrected, un-hardcode this MTRR. @@ -75,6 +70,7 @@ static void amd_initmmio(void) asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + enable_pci_mmconf(); amd_initmmio(); /* * Call lib/bootblock.c main with BSP, shortcut for APs -- cgit v1.2.3