From 66ff4fb1a565fe5f040e893bd02e52fed3ad2771 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 8 Aug 2023 12:28:03 -0500 Subject: soc/amd/stoneyridge: use SoC common uart ops Define the UARTs as MMIO devices in the chipset devicetrees. Drop ACPI _STA in asl since now handled by common SSDT generator. Implement wait_for_aoac_enabled() since required by SoC common code, and ensure compiled during all stages necessary. TEST=build/boot google/liara, verify console UART still functional. Change-Id: Ibecafdfa189d9c63a29b63759c5b965d03719009 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/77093 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/aoac.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/amd/stoneyridge/aoac.c') diff --git a/src/soc/amd/stoneyridge/aoac.c b/src/soc/amd/stoneyridge/aoac.c index 7c1d12ddc1..505b2c80f6 100644 --- a/src/soc/amd/stoneyridge/aoac.c +++ b/src/soc/amd/stoneyridge/aoac.c @@ -21,6 +21,12 @@ static const unsigned int aoac_devs[] = { FCH_AOAC_DEV_I2C3, }; +void wait_for_aoac_enabled(unsigned int dev) +{ + while (!is_aoac_device_enabled(dev)) + udelay(100); +} + void enable_aoac_devices(void) { bool status; -- cgit v1.2.3