From ae7ac8a72372e4099bcf0667b5f97b4a223da48d Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 12 Jan 2021 15:23:25 +0200 Subject: ACPI: Separate ChromeOS NVS in ASL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there is reduced dsdt.aml size and reduced GNVS allocation from cbmem. More importantly, it's less error-prone when the OperationRegion size is not hard-coded inside the .asl files. Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/acpi/globalnvs.asl | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/soc/amd/stoneyridge/acpi') diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index 252ceda911..7a48dd57f8 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -42,7 +42,4 @@ Field (GNVS, ByteAcc, NoLock, Preserve) FW01, 32, // 0x28 - xHCI FW RAM addr, boot RAM FW03, 32, // 0x2c - xHCI FW RAM addr, Instruction RAM EH10, 32, // 0x30 - EHCI BAR - /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ - Offset (0x100), - #include } -- cgit v1.2.3