From 31c8cdda73461f59a29457e482934cd686feed39 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Thu, 9 Nov 2017 12:23:47 -0700 Subject: soc/amd/stoneyridge: Add GNVS variables for thermal control BUG=b:67999819 Change-Id: I78db830c14092f5e918657e62bf38ab7124b1646 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/22398 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Marshall Dawson --- src/soc/amd/stoneyridge/acpi/globalnvs.asl | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/amd/stoneyridge/acpi') diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index bf0ed55249..7e696aa816 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -41,6 +41,12 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PRT0, 32, // 0x25 - 0x28 - PERST_0 Address SCDP, 8, // 0x29 - SD_CD GPIO portid SCDO, 8, // 0x2A - GPIO pad offset relative to the community + TMPS, 8, // 0x2B - Temperature Sensor ID + TLVL, 8, // 0x2C - Throttle Level Limit + FLVL, 8, // 0x2D - Current FAN Level + TCRT, 8, // 0x2E - Critical Threshold + TPSV, 8, // 0x2F - Passive Threshold + TMAX, 8, // 0x30 - CPU Tj_max /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include -- cgit v1.2.3