From 26f97f9532933da3c1d72a7918c8a24457bbc1c0 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 1 Oct 2021 14:53:22 -0600 Subject: src/soc to src/superio: Fix spelling errors These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082 Reviewed-by: Felix Held Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/amd/stoneyridge/acpi') diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 78ce889e5d..f7ea782da9 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -56,7 +56,7 @@ Name(CRES, ResourceTemplate() { * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ -- cgit v1.2.3