From 6744dfe7e0ac6a5b8c8cbe08126e1dec2e74aecd Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Wed, 14 Jun 2017 16:09:07 -0600 Subject: soc/amd/stoneyridge/acpi: Fix checkpatch errors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Correct the checkpatch errors reported in the asl files and make other stylistic modifications. These changes were confirmed to cause no changes in a Gardenia build. BUG=chrome-os-partner:622407746 Change-Id: Id8b2620d161062c444e493325d83bb158705b76b Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/20248 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Philippe Mathieu-Daudé --- src/soc/amd/stoneyridge/acpi/usb.asl | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'src/soc/amd/stoneyridge/acpi/usb.asl') diff --git a/src/soc/amd/stoneyridge/acpi/usb.asl b/src/soc/amd/stoneyridge/acpi/usb.asl index fd3ff54f7d..b2e5f4914d 100644 --- a/src/soc/amd/stoneyridge/acpi/usb.asl +++ b/src/soc/amd/stoneyridge/acpi/usb.asl @@ -17,49 +17,49 @@ /* 0:12.0 - OHCI */ Device(UOH1) { Name(_ADR, 0x00120000) - Name(_PRW, Package() {0x0B, 3}) + Name(_PRW, Package() {0x0b, 3}) } /* end UOH1 */ /* 0:12.2 - EHCI */ Device(UOH2) { Name(_ADR, 0x00120002) - Name(_PRW, Package() {0x0B, 3}) + Name(_PRW, Package() {0x0b, 3}) } /* end UOH2 */ /* 0:13.0 - OHCI */ Device(UOH3) { Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) + Name(_PRW, Package() {0x0b, 3}) } /* end UOH3 */ /* 0:13.2 - EHCI */ Device(UOH4) { Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) + Name(_PRW, Package() {0x0b, 3}) } /* end UOH4 */ /* 0:16.0 - OHCI */ Device(UOH5) { Name(_ADR, 0x00160000) - Name(_PRW, Package() {0x0B, 3}) + Name(_PRW, Package() {0x0b, 3}) } /* end UOH5 */ /* 0:16.2 - EHCI */ Device(UOH6) { Name(_ADR, 0x00160002) - Name(_PRW, Package() {0x0B, 3}) + Name(_PRW, Package() {0x0b, 3}) } /* end UOH5 */ /* 0:10.0 - XHCI 0*/ Device(XHC0) { Name(_ADR, 0x00100000) - Name(_PRW, Package() {0x0B, 4}) + Name(_PRW, Package() {0x0b, 4}) } /* end XHC0 */ #if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN /* 0:10.1 - XHCI 1*/ Device(XHC1) { Name(_ADR, 0x00100001) - Name(_PRW, Package() {0x0B, 4}) + Name(_PRW, Package() {0x0b, 4}) } /* end XHC1 */ #endif -- cgit v1.2.3