From 22f54c5a81bf387edcd7ea792bc1717c554054c6 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Wed, 29 Nov 2017 09:30:23 -0700 Subject: amd/stoneyridge: Add NV storage to ramtop The scratch registers in northbridge used for storing the top of cacheable memory are volatile. Use the BiosRam storage in the FCH instead. TEST=Suspend and resume Kahlee with complete S3 patch stack BUG=b:69614064 Change-Id: Ieb3cfd173c70bf899a6391d62d1df87b38485f30 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/22726 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/amd/stoneyridge/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/amd/stoneyridge/Makefile.inc') diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index e043caf63a..9f99c3c58d 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -47,6 +47,7 @@ bootblock-y += reset.c bootblock-y += sb_util.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c +bootblock-y += sb_util.c romstage-y += BiosCallOuts.c romstage-y += i2c.c @@ -76,6 +77,7 @@ verstage-y += tsc_freq.c postcar-y += monotonic_timer.c postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c postcar-y += ramtop.c +postcar-y += sb_util.c ramstage-y += BiosCallOuts.c ramstage-y += i2c.c -- cgit v1.2.3