From ed69450d621ec9a73a9a7009ebbdade6fa7333e4 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Wed, 22 Jun 2022 15:09:23 +0200
Subject: soc/amd/sabrina/Kconfig: set soft fuse bit 34

The bits are documented in NDA document #55758.

BUG=b:228458221

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibc27f617ca9c9620b3b2cb0837b661fa0cd36c2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
---
 src/soc/amd/sabrina/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/soc/amd/sabrina')

diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig
index bffb73fc28..ecb5dd4cd7 100644
--- a/src/soc/amd/sabrina/Kconfig
+++ b/src/soc/amd/sabrina/Kconfig
@@ -403,7 +403,7 @@ config SPL_TABLE_FILE
 
 config PSP_SOFTFUSE_BITS
 	string "PSP Soft Fuse bits to enable"
-	default "28 6"
+	default "34 28 6"
 	help
 	  Space separated list of Soft Fuse bits to enable.
 	  Bit 0:  Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)
-- 
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