From 615818f5a98d19079fd5e1725cd56786d39882c2 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 31 May 2022 21:33:43 +0200 Subject: soc/amd/*: Make mtrr decision based on syscfg The syscfg has to option to automatically mark the range between 4G and TOM2, which contains DRAM, as WB. Making it generally not necessary to allocate MTRRs for memory above 4G if no PCI BARs are placed up there. Change-Id: Ifbacae28e272ab2f39f268ad034354a9c590d035 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/64868 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/sabrina/cpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/soc/amd/sabrina') diff --git a/src/soc/amd/sabrina/cpu.c b/src/soc/amd/sabrina/cpu.c index addbf7ec18..462fb0d6fd 100644 --- a/src/soc/amd/sabrina/cpu.c +++ b/src/soc/amd/sabrina/cpu.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -33,7 +34,11 @@ _Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the nu */ static void pre_mp_init(void) { - x86_setup_mtrrs_with_detect_no_above_4gb(); + const msr_t syscfg = rdmsr(SYSCFG_MSR); + if (syscfg.lo & SYSCFG_MSR_TOM2WB) + x86_setup_mtrrs_with_detect_no_above_4gb(); + else + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); } -- cgit v1.2.3