From ba21a1f76c363f752b82c569b787bfde3337535e Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 19 Jan 2022 22:06:11 +0100 Subject: soc/amd/sabrina: drop PM_ESPI_CS_USE_DATA2 define and eSPI util code The Sabrina SoC doesn't have the PM_ESPI_CS_USE_DATA2 bit defined in the PM_SPI_PAD_PU_PD register. It also doesn't have a physical LPC interface any more, so there are no LPC pins that can be reconfigured as eSPI interface. Signed-off-by: Felix Held Change-Id: I02bc8d007901c71942475fe707637c5da7227230 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61097 Tested-by: build bot (Jenkins) Reviewed-by: Fred Reitberger Reviewed-by: Jason Glenesk Reviewed-by: Marshall Dawson --- src/soc/amd/sabrina/include/soc/espi.h | 11 ----------- src/soc/amd/sabrina/include/soc/southbridge.h | 1 - 2 files changed, 12 deletions(-) delete mode 100644 src/soc/amd/sabrina/include/soc/espi.h (limited to 'src/soc/amd/sabrina/include') diff --git a/src/soc/amd/sabrina/include/soc/espi.h b/src/soc/amd/sabrina/include/soc/espi.h deleted file mode 100644 index 7edef44611..0000000000 --- a/src/soc/amd/sabrina/include/soc/espi.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Check if this is still correct */ - -#ifndef AMD_SABRINA_ESPI_H -#define AMD_SABRINA_ESPI_H - -void espi_disable_lpc_ldrq(void); -void espi_switch_to_spi2_pads(void); - -#endif /* AMD_SABRINA_ESPI_H */ diff --git a/src/soc/amd/sabrina/include/soc/southbridge.h b/src/soc/amd/sabrina/include/soc/southbridge.h index 4ce58dd9d1..869af0bc87 100644 --- a/src/soc/amd/sabrina/include/soc/southbridge.h +++ b/src/soc/amd/sabrina/include/soc/southbridge.h @@ -75,7 +75,6 @@ #define PM_ACPI_USE_GATED_ALINK_CLK BIT(30) #define PM_ACPI_DELAY_GPP_OFF_TIME BIT(31) #define PM_SPI_PAD_PU_PD 0x90 -#define PM_ESPI_CS_USE_DATA2 BIT(16) #define PM_LPC_GATING 0xec #define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_A20_EN BIT(1) -- cgit v1.2.3