From 8d2bfbce23f6ff53cd8014286645a408886549a1 Mon Sep 17 00:00:00 2001 From: Fred Reitberger Date: Tue, 7 Jun 2022 11:34:28 -0400 Subject: soc/amd/sabrina/acpi: Correct VID decoding on Sabrina Sabrina uses the SVI3 spec for VID tables which is incompatible with the SVI2 spec used on PCO/CZN. Move the defines from common to soc and update the decoding for sabrina. See NDA docs #56413 for SVI3 and #48022 for SVI2 VID tables TEST=timeless builds on mandolin/majolica for PCO/CZN build chausie and verify pstate power is correct in ACPI tables Signed-off-by: Fred Reitberger Change-Id: I915e962f11615246690c6be1bee3533336a808f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65001 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/sabrina/include/soc/msr.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/amd/sabrina/include') diff --git a/src/soc/amd/sabrina/include/soc/msr.h b/src/soc/amd/sabrina/include/soc/msr.h index bdc7a14c40..9dba2697e2 100644 --- a/src/soc/amd/sabrina/include/soc/msr.h +++ b/src/soc/amd/sabrina/include/soc/msr.h @@ -21,6 +21,10 @@ #define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT) #define PSTATE_DEF_LO_CORE_FREQ_BASE 25 +/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */ +#define SERIAL_VID_DECODE_MICROVOLTS 5000 +#define SERIAL_VID_BASE_MICROVOLTS 245000L + #define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7 #define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8 -- cgit v1.2.3