From a05f518dea5fe700d99dcce1882739a15427a0d9 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 10 Jun 2022 21:04:36 +0200 Subject: soc/amd/sabrina: only make the available clock outputs configurable Sabrina only has 4 PCIe clock outputs with corresponding clock request pins available, so only make those 4 configurable in devicetree and disable the rest unconditionally. TEST=None Signed-off-by: Felix Held Change-Id: I5d34fa680dd20a6eec86cc278c1c901b3231df83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65089 Tested-by: build bot (Jenkins) Reviewed-by: Fred Reitberger Reviewed-by: Raul Rangel --- src/soc/amd/sabrina/chip.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/amd/sabrina/chip.h') diff --git a/src/soc/amd/sabrina/chip.h b/src/soc/amd/sabrina/chip.h index c272f9f2dc..3662605964 100644 --- a/src/soc/amd/sabrina/chip.h +++ b/src/soc/amd/sabrina/chip.h @@ -90,7 +90,7 @@ struct soc_amd_sabrina_config { GPP_CLK_ON, /* GPP clock always on; default */ GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ GPP_CLK_OFF, /* GPP clk off */ - } gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; + } gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE]; /* performance policy for the PCIe links: power consumption vs. link speed */ enum { -- cgit v1.2.3