From 556d1cc17f34615e3a08ccc9a48820a304a789a8 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 2 Feb 2022 22:11:52 +0100 Subject: soc/amd/*/i2c: factor out common I2C pad configuration The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/sabrina/chip.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/soc/amd/sabrina/chip.h') diff --git a/src/soc/amd/sabrina/chip.h b/src/soc/amd/sabrina/chip.h index a7acb7f29f..c272f9f2dc 100644 --- a/src/soc/amd/sabrina/chip.h +++ b/src/soc/amd/sabrina/chip.h @@ -6,6 +6,7 @@ #define SABRINA_CHIP_H #include +#include #include #include #include @@ -17,7 +18,7 @@ struct soc_amd_sabrina_config { struct soc_amd_common_config common_config; u8 i2c_scl_reset; struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT]; - u8 i2c_pad_ctrl_rx_sel[I2C_CTRLR_COUNT]; + struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT]; /* Enable S0iX support */ bool s0ix_enable; -- cgit v1.2.3