From e8ffa9ffd3cf5cb9fcade12e1f1e0dea5fc3fcf2 Mon Sep 17 00:00:00 2001
From: Marshall Dawson <marshall.dawson@amd.corp-partner.google.com>
Date: Mon, 16 Mar 2020 19:20:20 -0600
Subject: soc/amd/psp: Add SmmInfo command

Implement the MboxBiosCmdSmmInfo function to inform the PSP of the SoC's
SMM configuration. Once the BootDone command is sent, the PSP only
responds to commands where the buffer is in SMM memory.

Set aside a region for the core-to-PSP command buffer and the
PSP-to-core mailbox. Also add an SMM flag, which the PSP expects to read
as non-zero during an SMI.

Add calls to soc functions for the soc to populate the trigger info and
register info (v2 only).

Add functions to set up the structures needed for the SmmInfo function
in Picasso support. Issue a SW SMI, and add a new handler to call the
new PSP function.

BUG=b:153677737

Change-Id: I10088a53e786db788740e4b388650641339dae75
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
---
 src/soc/amd/picasso/include/soc/smi.h |  3 +++
 src/soc/amd/picasso/psp.c             | 39 +++++++++++++++++++++++++++++++++++
 src/soc/amd/picasso/smi.c             |  3 +++
 src/soc/amd/picasso/smihandler.c      |  4 ++++
 4 files changed, 49 insertions(+)

(limited to 'src/soc/amd/picasso')

diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h
index e890e1319a..fb8061ca16 100644
--- a/src/soc/amd/picasso/include/soc/smi.h
+++ b/src/soc/amd/picasso/include/soc/smi.h
@@ -86,6 +86,7 @@
 #define SMITYPE_NB_GPP_HOT_PLUG		30
 /* 31 Reserved */
 #define SMITYPE_WAKE_L2			32
+#define SMITYPE_PSP			33
 /* 33 - 38 Reserved */
 #define SMITYPE_AZPME			39
 #define SMITYPE_USB_PD_I2C4		40
@@ -186,6 +187,8 @@
 #define SMI_REG_CONTROL8		0xc0
 #define SMI_REG_CONTROL9		0xc4
 
+#define SMI_MODE_MASK			0x03
+
 enum smi_mode {
 	SMI_MODE_DISABLE = 0,
 	SMI_MODE_SMI = 1,
diff --git a/src/soc/amd/picasso/psp.c b/src/soc/amd/picasso/psp.c
index d6eb7d31a3..88b25b88b0 100644
--- a/src/soc/amd/picasso/psp.c
+++ b/src/soc/amd/picasso/psp.c
@@ -3,6 +3,8 @@
 
 #include <console/console.h>
 #include <cpu/x86/msr.h>
+#include <soc/smi.h>
+#include <amdblocks/acpimmio_map.h>
 #include <amdblocks/psp.h>
 
 #define PSP_MAILBOX_OFFSET		0x10570
@@ -20,3 +22,40 @@ void *soc_get_mbox_address(void)
 
 	return (void *)(psp_mmio + PSP_MAILBOX_OFFSET);
 }
+
+void soc_fill_smm_trig_info(struct smm_trigger_info *trig)
+{
+	if (!trig)
+		return;
+
+	trig->address = 0xfed802a8;
+	trig->address_type = SMM_TRIGGER_MEM;
+	trig->value_width = SMM_TRIGGER_DWORD;
+	trig->value_and_mask = 0xfdffffff;
+	trig->value_or_mask = 0x02000000;
+}
+
+void soc_fill_smm_reg_info(struct smm_register_info *reg)
+{
+	if (!reg)
+		return;
+
+	reg->smi_enb.address = ACPIMMIO_SMI_BASE + SMI_REG_SMITRIG0;
+	reg->smi_enb.address_type = SMM_TRIGGER_MEM;
+	reg->smi_enb.value_width = SMM_TRIGGER_DWORD;
+	reg->smi_enb.reg_bit_mask = SMITRG0_SMIENB;
+	reg->smi_enb.expect_value = 0;
+
+	reg->eos.address = ACPIMMIO_SMI_BASE + SMI_REG_SMITRIG0;
+	reg->eos.address_type = SMM_TRIGGER_MEM;
+	reg->eos.value_width = SMM_TRIGGER_DWORD;
+	reg->eos.reg_bit_mask = SMITRG0_EOS;
+	reg->eos.expect_value = SMITRG0_EOS;
+
+	reg->psp_smi_en.address = ACPIMMIO_SMI_BASE + SMI_REG_CONTROL0;
+	reg->psp_smi_en.address += sizeof(uint32_t) * SMITYPE_PSP / 16;
+	reg->psp_smi_en.address_type = SMM_TRIGGER_MEM;
+	reg->psp_smi_en.value_width = SMM_TRIGGER_DWORD;
+	reg->psp_smi_en.reg_bit_mask = SMI_MODE_MASK << (2 * SMITYPE_PSP % 16);
+	reg->psp_smi_en.expect_value = SMI_MODE_SMI << (2 * SMITYPE_PSP % 16);
+}
diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c
index ab8f405e59..273c55b635 100644
--- a/src/soc/amd/picasso/smi.c
+++ b/src/soc/amd/picasso/smi.c
@@ -17,6 +17,7 @@
  * Utilities for SMM setup
  */
 
+#include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <amdblocks/acpimmio.h>
@@ -35,4 +36,6 @@ void enable_smi_generation(void)
 	reg &= ~SMITRG0_SMIENB;	/* Enable SMI generation */
 	reg |= SMITRG0_EOS;	/* Set EOS bit */
 	smi_write32(SMI_REG_SMITRIG0, reg);
+
+	outb(APM_CNT_SMMINFO, APM_CNT);
 }
diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c
index 55493776dd..e4d1c86f57 100644
--- a/src/soc/amd/picasso/smihandler.c
+++ b/src/soc/amd/picasso/smihandler.c
@@ -26,6 +26,7 @@
 #include <soc/southbridge.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/acpi.h>
+#include <amdblocks/psp.h>
 #include <elog.h>
 
 /* bits in smm_io_trap   */
@@ -125,6 +126,9 @@ static void sb_apmc_smi_handler(void)
 		if (CONFIG(SMMSTORE))
 			southbridge_smi_store();
 		break;
+	case APM_CNT_SMMINFO:
+		psp_notify_smm();
+		break;
 	}
 
 	mainboard_smi_apmc(cmd);
-- 
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