From c5d71dc7ff9bc253a9151d1da9f55b0c59406820 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 20 Jan 2023 20:47:22 +0100 Subject: soc/amd/picasso: remove LIDS field from global NVS Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Picasso SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held Change-Id: Ia265f3eebf5e48c185d2e4bf4ef74f8eab7c9606 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72183 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/picasso/acpi/globalnvs.asl | 13 ++++++------- src/soc/amd/picasso/include/soc/nvs.h | 13 ++++++------- 2 files changed, 12 insertions(+), 14 deletions(-) (limited to 'src/soc/amd/picasso') diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index f616361ec6..2d24b888fd 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -9,11 +9,10 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - LIDS, 8, // 0x00 - LID State - CBMC, 32, // 0x01 - 0x04 - coreboot Memory Console - PM1I, 64, // 0x05 - 0x0c - System Wake Source - PM1 Index - GPEI, 64, // 0x0d - 0x14 - GPE Wake Source - TMPS, 8, // 0x15 - Temperature Sensor ID - TCRT, 8, // 0x16 - Critical Threshold - TPSV, 8, // 0x17 - Passive Threshold + CBMC, 32, // 0x00 - 0x03 - coreboot Memory Console + PM1I, 64, // 0x04 - 0x0b - System Wake Source - PM1 Index + GPEI, 64, // 0x0c - 0x13 - GPE Wake Source + TMPS, 8, // 0x14 - Temperature Sensor ID + TCRT, 8, // 0x15 - Critical Threshold + TPSV, 8, // 0x16 - Passive Threshold } diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index aef4a977b8..c5821bbb0b 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -14,13 +14,12 @@ struct __packed global_nvs { /* Miscellaneous */ - uint8_t lids; /* 0x00 - LID State */ - uint32_t cbmc; /* 0x01 - 0x04 - coreboot Memory Console */ - uint64_t pm1i; /* 0x05 - 0x0c - System Wake Source - PM1 Index */ - uint64_t gpei; /* 0x0d - 0x14 - GPE Wake Source */ - uint8_t tmps; /* 0x15 - Temperature Sensor ID */ - uint8_t tcrt; /* 0x16 - Critical Threshold */ - uint8_t tpsv; /* 0x17 - Passive Threshold */ + uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */ + uint64_t pm1i; /* 0x04 - 0x0b - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x0c - 0x13 - GPE Wake Source */ + uint8_t tmps; /* 0x14 - Temperature Sensor ID */ + uint8_t tcrt; /* 0x15 - Critical Threshold */ + uint8_t tpsv; /* 0x16 - Passive Threshold */ }; #endif /* AMD_PICASSO_NVS_H */ -- cgit v1.2.3