From c2cee06b4efb8992e625ca4554df17c7ef457930 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 12 Oct 2021 23:35:11 +0200 Subject: soc/amd/common/block/i2c: implement proper read_resource Before this patch the reservation of the MMIO region of the I2C controllers was done in the LPC controller PCI device despite the I2C controllers already being devices in the devicetree. This patch implements this functionality as read_resources function of the I2C device instead. This will only reserve the memory when the I2C devices are enabled in devicetree which is a change from the previous behavior. Signed-off-by: Felix Held Change-Id: I67c853df3be2f593ecfa113ae2f74e5df7cf74e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58307 Reviewed-by: Raul Rangel Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/include/soc/iomap.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'src/soc/amd/picasso') diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index c56e7af736..1577568c90 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -48,11 +48,6 @@ #define APU_I2C3_BASE 0xfedc5000 #define APU_I2C4_BASE 0xfedc6000 -/* I2C parameters for lpc_read_resources */ -#define I2C_BASE_ADDRESS APU_I2C2_BASE -#define I2C_DEVICE_SIZE 0x00001000 -#define I2C_DEVICE_COUNT (I2C_MASTER_DEV_COUNT - I2C_MASTER_START_INDEX) - #define APU_DMAC0_BASE 0xfedc7000 #define APU_DMAC1_BASE 0xfedc8000 #define APU_UART0_BASE 0xfedc9000 -- cgit v1.2.3