From 906f9be383c9c8258d4c0b6abc6dfebf16aa65e5 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 13 Feb 2021 20:38:08 +0100 Subject: soc/amd/common/block/data_fabric: add data_fabric_print_mmio_conf Output on Picasso at the beginning of data_fabric_set_mmio_np: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 93 fc00 febf 1 93 1000000 ffffffff 2 93 d000 f7ff 3 90 0 0 4 93 fed0 fed0 5 90 0 0 6 90 0 0 7 90 0 0 Output on Picasso at the end of data_fabric_set_mmio_np: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 93 fc00 febf 1 93 1000000 ffffffff 2 93 d000 f7ff 3 1093 fed0 fedf 4 90 0 0 5 90 0 0 6 90 0 0 7 90 0 0 Signed-off-by: Felix Held Change-Id: I74617dfc6099489f3c81d0e385b502f1bbecea78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50640 Reviewed-by: Marshall Dawson Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/data_fabric.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/amd/picasso') diff --git a/src/soc/amd/picasso/data_fabric.c b/src/soc/amd/picasso/data_fabric.c index d07555a437..982b7b243d 100644 --- a/src/soc/amd/picasso/data_fabric.c +++ b/src/soc/amd/picasso/data_fabric.c @@ -39,6 +39,8 @@ void data_fabric_set_mmio_np(void) const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; const uint32_t np_top = (LOCAL_APIC_ADDR - 1) >> D18F0_MMIO_SHIFT; + data_fabric_print_mmio_conf(); + for (i = 0; i < NUM_NB_MMIO_REGS; i++) { /* Adjust all registers that overlap */ ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); @@ -92,6 +94,8 @@ void data_fabric_set_mmio_np(void) data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), (IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT) | MMIO_NP | MMIO_WE | MMIO_RE); + + data_fabric_print_mmio_conf(); } static const char *data_fabric_acpi_name(const struct device *dev) -- cgit v1.2.3