From 73a544d4533fa8305f1c0a809137b5e2151ea17e Mon Sep 17 00:00:00 2001 From: Michał Żygowski Date: Sun, 24 Nov 2019 14:16:34 +0100 Subject: soc/amd/common/block/acpimmio: fix ACPIMMIO decode enable function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to BKDGs for families 15h 60-6fh or newer and families 16h the ACPI MMIO decode enable bit is the second LSB, not the first LSB. Additionally create another enable function for older families where the register and bit is different. It does not seem to impact any current board, but may be crucial for incoming C bootblock implementations when this bit will need to be set very early. Most likely this bit is set by AGESA right now. Signed-off-by: Michał Żygowski Change-Id: Iaa31abc3dbdf77d8513fa83c7415b9a1b7fd266f Reviewed-on: https://review.coreboot.org/c/coreboot/+/37178 Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/southbridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/amd/picasso') diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index fe801d4126..041d262af7 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -278,7 +278,7 @@ void fch_pre_init(void) sb_disable_4dw_burst(); sb_set_spi100(SPI_SPEED_33M, SPI_SPEED_33M, SPI_SPEED_16M, SPI_SPEED_16M); - enable_acpimmio_decode(); + enable_acpimmio_decode_pm04(); fch_smbus_init(); sb_enable_cf9_io(); sb_enable_legacy_io(); -- cgit v1.2.3