From 64d0ad347b5c9c698547f0ff15779e88a10014f4 Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Mon, 21 Dec 2020 13:56:22 +0800 Subject: soc/amd: Add an option to select if SOC supports ESPI sub decode Cezanne doesn't have eSPIx00034 register define in PPR. Currently only Picasso need this option. Change-Id: Icb8e8a1a59393849395125108bfaa884839ce10f Signed-off-by: Zheng Bao Reviewed-on: https://review.coreboot.org/c/coreboot/+/48842 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/picasso/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/amd/picasso') diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index da3903bfbd..93d2ef80c4 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -29,6 +29,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_HAS_ESPI + select SOC_AMD_COMMON_BLOCK_HAS_ESPI_SUB_DECODE select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS -- cgit v1.2.3