From 5c5f211b5b6e042637cf0256d2040ea66dadc8e9 Mon Sep 17 00:00:00 2001
From: Raul E Rangel <rrangel@chromium.org>
Date: Thu, 11 Feb 2021 16:00:22 -0700
Subject: soc/amd: Move aoac.asl from picasso into common

I also removed the unnecessary #include in soc.asl.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifbd79871fd49b18f45d97f64ccd68fa96eaaebce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50572
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/picasso/acpi/aoac.asl   | 115 ------------------------------------
 src/soc/amd/picasso/acpi/sb_fch.asl |   2 +-
 src/soc/amd/picasso/acpi/soc.asl    |   3 -
 3 files changed, 1 insertion(+), 119 deletions(-)
 delete mode 100644 src/soc/amd/picasso/acpi/aoac.asl

(limited to 'src/soc/amd/picasso')

diff --git a/src/soc/amd/picasso/acpi/aoac.asl b/src/soc/amd/picasso/acpi/aoac.asl
deleted file mode 100644
index d7523dfe23..0000000000
--- a/src/soc/amd/picasso/acpi/aoac.asl
+++ /dev/null
@@ -1,115 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#define AOAC_DEVICE(DEV_ID, SX) \
-	PowerResource(AOAC, SX, 0) { \
-		OperationRegion (AOAC, SystemMemory, ACPIMMIO_BASE(AOAC) + 0x40 + (DEV_ID << 1), 2) \
-		Field (AOAC, ByteAcc, NoLock, Preserve) { \
-			/* \
-			 * Target Device State \
-			 * \
-			 * 0 = D0 - Uninitialized \
-			 * 1 = D0 - Initialized \
-			 * 2 = D1/D2/D3Hot \
-			 * 3 = D3Cold \
-			 * \
-			 * This field is only used to cut off register access. It does not \
-			 * control any power states. D3Cold is the only value that will \
-			 * cut off register access. All other values will allow register \
-			 * access and are purely informational. \
-			 */ \
-			TDS,	2, \
-\
-			DS,	1, /* Device State - Purely informational */ \
-\
-			/* \
-			 * Power On Dev \
-			 * \
-			 * 1 = Perform hardware sequence to power on the device \
-			 * 0 = Perform hardware sequence to power off the device \
-			 * \
-			 * This register is only valid when Is Software Control = 0. \
-			 */ \
-			POD,	1, \
-\
-			/* Software Power On Reset B */ \
-			SPRB,	1, \
-			/* Software Ref Clock OK */ \
-			SRCO,	1, \
-			/* Software Reset B */ \
-			SRB,	1, \
-			/* \
-			 * Is Software Control \
-			 * \
-			 * 1 = Allow software to control Power On Reset B, \
-			 *     Ref Clock OK, and Reset B. \
-			 * 0 = Hardware control \
-			 */ \
-			ISWC,	1, \
-\
-			/* Power Reset B State */ \
-			PRBS,	1, \
-			/* Ref Clock OK State */ \
-			RCOS,	1, \
-			/* Reset B State */ \
-			RBS,	1, \
-			/* Device Off Gating State */ \
-			DOGS,	1, \
-			/* D3 Cold State */ \
-			D3CS,	1, \
-			/* Device Clock OK State */ \
-			COS,	1, \
-			/* State of device */ \
-			STA0,	1, \
-			/* State of device */ \
-			STA1,	1, \
-		} \
-		Method(_STA) { \
-			Local0 = (PRBS && RCOS && RBS) \
-\
-			If (Local0) { \
-				Return (1) \
-			} Else { \
-				Return (0) \
-			} \
-		} \
-		Method(_ON, 0, Serialized) { \
-			ISWC=0 \
-			POD=1 \
-\
-			While (!PRBS || !RCOS || !RBS) { \
-				Stall (100) \
-			} \
-		} \
-		Method(_OFF, 0, Serialized) { \
-			ISWC=0 \
-			POD=0 \
-\
-			While (PRBS || RCOS || RBS) { \
-				Stall (100) \
-			} \
-		} \
-		Method(_RST, 0, Serialized) { \
-			ISWC=1 \
-			SRB=1 \
-\
-			/* Assert the SwRstB signal for 200 us */ \
-			Stall (200) \
-\
-			SRB=0 \
-			ISWC=0 \
-\
-			While (!PRBS || !RCOS || !RBS) { \
-				Printf ("Waiting for device to complete reset") \
-				Stall (100) \
-			} \
-		} \
-	} \
-	Name (_PR0, Package () { AOAC }) \
-	Name (_PR2, Package () { AOAC }) \
-	Name (_PR3, Package () { AOAC }) \
-	Method (_PS0, 0, Serialized) { \
-		^AOAC.TDS = 1 \
-	} \
-	Method (_PS3, 0, Serialized) { \
-		^AOAC.TDS = 3 \
-	}
diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl
index 6c3c51dedf..926bf10c39 100644
--- a/src/soc/amd/picasso/acpi/sb_fch.asl
+++ b/src/soc/amd/picasso/acpi/sb_fch.asl
@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <soc/amd/common/acpi/aoac.asl>
 #include <soc/gpio.h>
 #include <soc/iomap.h>
 #include <amdblocks/acpimmio_map.h>
-#include <aoac.asl>
 
 Device (AAHB)
 {
diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl
index b3b036ea7d..b411c20ba4 100644
--- a/src/soc/amd/picasso/acpi/soc.asl
+++ b/src/soc/amd/picasso/acpi/soc.asl
@@ -11,9 +11,6 @@ Device(PCI0) {
 /* Describe PCI INT[A-H] for the Southbridge */
 #include "pci_int.asl"
 
-/* Describe the AOAC devices */
-#include "aoac.asl"
-
 /* Describe the devices in the Southbridge */
 #include "sb_fch.asl"
 
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