From 3eff037f8cbe99f72626c0f25c0989ea638599ef Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 10 Sep 2019 15:51:17 +0530 Subject: soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch removes dedicated function call to make TSEG region cache from soc and refers to postcar_enable_tseg_cache(). BUG=b:140008206 Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/35025 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Reviewed-by: Kyösti Mälkki --- src/soc/amd/picasso/romstage.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) (limited to 'src/soc/amd/picasso') diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 4f18b42276..9882d9115e 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -44,8 +44,6 @@ asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); console_init(); @@ -87,15 +85,8 @@ asmlinkage void car_stage_entry(void) /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + /* Cache the TSEG region */ + postcar_enable_tseg_cache(&pcf); post_code(0x45); run_postcar_phase(&pcf); -- cgit v1.2.3