From 1b5a7dec433b07d101897de65a45961a3aaf1114 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 12 Jul 2020 20:07:58 +0200 Subject: src: Drop useless PM1b settings from FADT None of the currently-supported chips has PM1b_EVT nor PM1b_CNT event register blocks. According to the ACPI specification, version 6.3, sections 4.8.1.1 and 4.8.1.2 (PM1 Event/Control Registers): If the PM1b_EVT_BLK is not supported, its pointer contains a value of zero in the FADT. If the PM1b_CNT_BLK is not supported, its pointer contains a value of zero in the FADT. Since the FADT struct defaults to zero in coreboot, we don't need to do anything with PM1b for now. So, drop unneeded writes to PM1b fields. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Iff788b2ff17ba190a8dd9b0b540f1ef059a1a0ea Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43380 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/acpi.c | 17 ----------------- 1 file changed, 17 deletions(-) (limited to 'src/soc/amd/picasso') diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index cc575ad7e9..afd9f48774 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -99,9 +99,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; - fadt->pm1b_evt_blk = 0x0000; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; - fadt->pm1b_cnt_blk = 0x0000; fadt->pm2_cnt_blk = 0x0000; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; fadt->gpe0_blk = ACPI_GPE0_BLK; @@ -159,14 +157,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; fadt->x_pm1a_evt_blk.addrh = 0x0; - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; @@ -174,13 +164,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - /* * Note: Under this current AMD C state implementation, this is no * longer used and should not be reported to OS. -- cgit v1.2.3