From 39a4ac1502b658d4ef6b57c50a0e386eff91364a Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 20 Jun 2019 16:28:33 -0600 Subject: soc/amd/picasso: Update southbridge Picasso's FCH has many similarities to Stoney Ridge, so few changes are necessary. The most notable changes are: * Update the index values for the C00/C01 interrupt routing * FORCE_STPCLK_RETRY is not present * PCIB is not defined * FCH MISC Registers 0xfed80e00 numbering has changed * C-state base moves from PM register to MSR * Add option to determine the intended MUX settion for LPC vs. eMMC * Remove the LEGACY_FREE option Signed-off-by: Marshall Dawson Change-Id: I69dfc4a875006639aa330385680d150331840e40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33770 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/picasso/smihandler.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src/soc/amd/picasso/smihandler.c') diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 9eddf853b6..4995acb484 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -163,7 +163,6 @@ static void sb_slp_typ_handler(void) /* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */ pci_ctrl = pm_read32(PM_PCI_CTRL); pci_ctrl &= ~FORCE_SLPSTATE_RETRY; - pci_ctrl |= FORCE_STPCLK_RETRY; pm_write32(PM_PCI_CTRL, pci_ctrl); /* Enable SlpTyp */ -- cgit v1.2.3